74LVC373APW,118 NXP Semiconductors, 74LVC373APW,118 Datasheet - Page 10

• Manufacturer Part Number: 74LVC373APW,118
• Description: IC OCTAL TRANSP LATCH 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC373APW,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 1.5ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: 74LVC
• Polarity: Non-Inverting
• Input Bias Current (max): 0.1 uA
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 9 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Technology: CMOS
• Package Type: TSSOP
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2304-2; 74LVC373APW-T; 935218650118

Philips Semiconductors
Notes
1. Typical values are measured at V
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
AC WAVEFORMS
2003 May 19
T
t
t
t
t
t
t
t
SYMBOL
PHL
PZH
PHZ
W
su
h
sk(0)
amb
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
V
V
V
by design.
M
M
OL
/t
/t
/t
PLH
= 1.5 V at V
= 0.5 V
PZL
PLZ
= 40 to +125 C
and V
OH
CC
propagation delay Dn to Qn see Figs 8 and 12
propagation delay LE to Qn see Figs 9 and 12
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
LE pulse width HIGH
set-up time Dn to LE
hold time Dn to LE
skew
are the typical output voltage drop that occur with the output load.
at V
CC
CC
2.7 V;
< 2.7 V.
PARAMETER
handbook, halfpage
Fig.8 Input (Dn) to output (Qn) propagation delays.
Qn output
Dn input
CC
= 3.3 V and T
see Figs 10 and 12 2.7
see Figs 10 and 12 2.7
see Fig.9
see Fig.11
see Fig.11
note 2
WAVEFORMS
GND
V OH
V OL
V I
TEST CONDITIONS
amb
10
= 25 C.
V M
V M
t PHL
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
V
CC
(V)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.5
4.5
2.0
2.0
1.5
1.5
MNA884
MIN.
t PLH
TYP.
Product specification
74LVC373A
10.0
8.5
10.5
9.0
11.0
10.0
9.0
8.0
1.5
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT