FM18L08-70-SG RAMTRON [Ramtron International Corporation], FM18L08-70-SG Datasheet - Page 2

• Manufacturer Part Number: FM18L08-70-SG
• Description: 256Kb Bytewide FRAM Memory
• Manufacturer: RAMTRON [Ramtron International Corporation]

Pin Description
Functional Truth Table
Note: The /OE pin controls only the DQ output buffers.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.4
July 2007
Pin Name
A0-A14
DQ0-7
/CE
/OE
/WE
VDD
VSS
/CE
H
L
L
WE
OE
CE
A0-A14
Supply
Supply
Type
Input
Input
Input
Input
I/O
/WE
X
X
H
Address
Pin Description
Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The
address value is latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the FRAM array.
Chip Enable. /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
Supply Voltage
Ground
Latch
Control
Logic
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
Write
A10-A14
A0-A7
A8-A9
Figure 1. Block Diagram
Decoder
Row
32,768 x 8 FRAM Array
Column Decoder
Block Decoder
Bus Driver
I/O Latch
1850 Ramtron Drive, Colorado Springs, CO 80921
Ramtron International Corporation
(800) 545-FRAM, [phone]
http://www.ramtron.com
DQ0-7
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