EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet
EVAL-ADAU1701EB
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EVAL-ADAU1701EB Summary of contents
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Preliminary Technical Data FEATURES 28/56-bit, 50 MHz digital audio processor Stereo ADC: 100 dB SNR and -80 dB THD+N 4-channel DAC: 104 dB SNR and -90 dB THD+N Complete stand-alone operation • Self-boot from serial EEPROM • Auxiliary ADC with ...
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ADAU1701 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 4 Analog Performance .................................................................... 4 Digital I/O ..................................................................................... 5 Power.............................................................................................. 5 Temperature Range ...................................................................... 5 Digital Timing............................................................................... 5 PLL ................................................................................................. 6 ...
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Preliminary Technical Data 4/06—Preliminary Version PrF Rev. PrF | Page ADAU1701 ...
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ADAU1701 SPECIFICATIONS Table 1. Test conditions, unless otherwise noted Parameter Conditions Analog Supply Voltage (AVDD) 3.3 V Digital Supply Voltage (DVDD) 1.8 V PLL Voltage (PVDD) 3.3 V Input/Output Voltage (IOVDD) 3.3 V Ambient Temperature 25° C Master Clock Input ...
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Preliminary Technical Data Parameter Gain Error DC Bias Power Supply Rejection DIGITAL I/O Table 3. Digital I/O Parameter Input Voltage Input Voltage Input Leakage Input Leakage ...
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ADAU1701 t SDATA_INx Setup SIS t SDATA_INx Hold SIH t OUTPUT_LRCLK Setup LOS t OUTPUT_LRCLK Hold LOH OUTPUT_BCLK Falling OUTPUT_LRCLK Timing Skew t SDATA_OUTx Delay SODS t SDATA_OUTx Delay SODM SPI PORT t CCLK Pulse Width LO ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 9. Parameter DVDD to GND AVDD to GND IOVDD to GND Digital Inputs Maximum Junction Temperature Storage Temperature Range Soldering (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent ...
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ADAU1701 TYPICAL PERFORMANCE CHARACTERISTICS ADC Decimation filter Passband Ripple 48KHz 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Frequency Figure 2. ADC Passband Filter Response, fs=48 kHz ADC Decimation filter ...
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Preliminary Technical Data Figure 8. ADC Total Harmonic Distortion + Noise vs. frequency Figure 9. DAC frequency response with 1 kHz, -60 dBFS input Figure 10. DAC frequency response with 1 kHz, 0 dBFS input Figure 11. DAC Total Harmonic ...
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ADAU1701 PIN CONFIGURATION AND FUNCTIONS Table 11. Pin Function Descriptions 1 Pin No. Type Mnemonic 1 PWR AGND 2 A_IN ADC1 3 A_IN ADC_RES 4 A_IN ADC0 5 D_IN RESETB 6 D_IN SELFBOOT 7 D_IN ADDR0 8 D_IO MP4 9 ...
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Preliminary Technical Data 14 D_IO MP7 15 D_IO MP6 16 D_IO MP10 17 A_OUT VDRIVE 18 PWR IOVDD 19 D_IO MP11 20 D_IN ADDR1/CDATA/WB 21 D_IN CLATCH / WP 22 D_IO SDA/COUT 23 D_IO SCL/CCLK 24 PWR DVDD 25 PWR ...
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ADAU1701 34 PWR PVDD 35 A_OUT PLL_LF 36 PWR AVDD 37 PWR AGND 38 D_IN PLL_MODE0 39 D_IN PLL_MODE1 40 A_OUT CM 41 A_OUT FILTD 42 PWR AGND 43 A_OUT VOUT3 44 A_OUT VOUT2 45 A_OUT VOUT1 46 A_OUT VOUT0 ...
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Preliminary Technical Data OVERVIEW The core of the ADAU1701 is a 28-bit DSP (56-bit with double precision) optimized for audio processing. The program and parameter RAMs can be loaded with a custom audio processing signal flow built with ADI’s SigmaStudio ...
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ADAU1701 INITIALIZATION POWER-UP SEQUENCE The ADAU1701 has a built-in power-up sequence that initializes the contents of all internal RAMs on power-up or when the part is brought out of reset. After RESETB (positive edge-triggered) goes high, the contents of the ...
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Preliminary Technical Data kHz and 11.2896 MHz for f = 44.1 kHz. The crystal the oscillator circuit should be an AT-cut parallel resonance device operating at its fundamental frequency. Figure 16 shows the recommended ...
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ADAU1701 10 uF 100 nF DVDD VDRIVE Figure 18. Voltage Regulator Design Two specifications need to be taken into consideration when choosing a regulator transistor. First, the transistor’s current 3.3V amplification factor (h the transistor’s collector needs to be able ...
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Preliminary Technical Data TWO-CHANNEL AUDIO ADC The ADAU1701 has a two-channel Σ-Δ ADC. The SNR of the ADCs is 100 dB and the THD+N is -80 dB. The stereo audio ADCs are current-input voltage-to- current resistor is required ...
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ADAU1701 FOUR-CHANNEL AUDIO DAC The ADAU1701’s main output is a four-channel Σ-Δ DAC. The SNR of the DAC is 104 dB and the THD+N is -90 dB. A full- scale output on the DACs is 0.9 Vrms (2.5 Vp-p). The ...
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Preliminary Technical Data CONTROL PORT OVERVIEW The ADAU1701 can operate in one of three control modes: • Control • SPI Control • Selfboot (no external controller) The ADAU1701 has both a 4-wire SPI control port, and a ...
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ADAU1701 line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/ W bit determines the direction ...
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Preliminary Technical Data Subaddress The 12-bit Subaddress word is decoded into a location in one of the memories or registers. This subaddress is the location of the appropriate RAM location or register. Data Bytes The number of data bytes varies ...
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ADAU1701 S Chip Address, AS Subaddress High R Chip Address, AS Subaddres s High R Chip AS Subaddress Address, High R Chip AS Subaddress Address, R/W High = ...
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Preliminary Technical Data SELF BOOT On power-up, the ADAU1701 can load a set of program and parameters that are saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this eliminates the need for a microcontroller ...
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ADAU1701 DSP Core Control Register. The parameter settings that should be saved are configured in SigmaStudio. The writeback functions by writing data from the ADAU1701’s interface registers to the second page of the selfboot EEPROM, addresses 32-63. Starting at EEPROM ...
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Preliminary Technical Data SIGNAL PROCESSING OVERVIEW The ADAU1701 is designed to provide all signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using the ADI- supplied SigmaStudio software, which allows graphical entry ...
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ADAU1701 RAMS AND REGISTERS Table 21. Control Port Addresses 2 SPI Subaddress Register/RAM Name 0–1023 (0x0000–0x03FF) Parameter RAM 1024–2047 (0x0400-0x07FF) Program RAM 2048-2055 (0x0800-0x0807) Interface Registers 2056 (0x0808) GPIO Pin Setting Register 2057-2060 (0x0809-0x080C) Aux ...
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Preliminary Technical Data The following sections discuss these two options in more detail. SAFELOAD REGISTERS Many applications require real-time microcontroller control of signal processing parameters, such as filter coefficients, mixer gains, multi-channel virtualizing parameters, or dynamics processing curves. One example ...
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ADAU1701 DSP CORE CONTROL REGISTER The controls in this register set the operation of the ADAU1701’s DSP core. Table 26. DSP Core Control Register (2076) Register Bits Function 15:14 Reserved 13:12 GPIO Debounce control 00 = 20ms 01 = 40ms ...
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Preliminary Technical Data microcontroller chips. In order to fit into a byte-oriented format, 0s are appended to the data fields before the MSB in order to extend the data word to the next multiple of eight bits. For example, 28-bit ...
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ADAU1701 2 RegSel[1:0] selects one of four registers (see Data Capture Registers section). Table 34. Data Capture (Control Port Readback) Register Read Format Byte 0 Byte 1 chip_adr [6:0], W/R 0000, data_capture_adr[11:8] Table 35. Safeload Address Register Write Format Byte ...
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Preliminary Technical Data MULTIPURPOSE PINS Table 37. Multipurpose Pin Configuration Registers Register Bits[23:20] MP_CFG0 (2080) MP5[3:0] MP_CFG1 (2081) MP11[3:0] The ADAU1701 has 12 multipurpose (MP) pins that can be individually programmed to be used as serial data inputs, serial data ...
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ADAU1701 20 kΩ Aux ADC Input Pin kΩ Figure 31. Auxiliary ADC input circuit Figure 31 shows the input circuit for the auxiliary ADC. Switch S1 enables the aux ADC, and is set by bit 15 of ...
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Preliminary Technical Data In TDM mode, the ADAU1701 can be a master for 48 kHz and 96 kHz data, but not for 192 kHz data. Table 43 displays the modes in which the serial output port will function. Table 43. ...
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ADAU1701 Table 46. Serial Output Control Register (2078) Register Bits Function 15:14 Unused 13 OUTPUT_LRCLK Polarity 0 = Frame Begins on Falling Edge 1 = Frame Begins on Rising Edge 12 OUTPUT_BCLK Polarity 0 = Data Changes on Falling Edge ...
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Preliminary Technical Data Table 47. Serial Input Control Register (2079) Register Bits Function 7:5 Unused 4 INPUT_LRCLK polarity 0 = Frame begins on falling edge 1 = Frame begins on rising edge 3 INPUT_BCLK polarity 0 = Data changes on ...
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ADAU1701 LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK BCLK DATA LRCLK BCLK MSB TDM SDATA CH 0 SLOT 0 SLOT 1 32 BCLKs LSB Figure 34. Right-Justified Mode— Bits per Channel 256 BCLKs 32 BCLKs ...
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Preliminary Technical Data LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage-to-current resistors and the ADC current set resistor should be placed as close to the input pins (2, 3 & possible. All 100 nF bypass capacitors, which are ...
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ADAU1701 TYPICAL APPLICATION SCHEMATIC – SELF BOOT MODE Preliminary Technical Data Rev. PrF | Page ...
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Preliminary Technical Data TYPICAL APPLICATION SCHEMATIC – CONTROL Rev. PrF | Page ADAU1701 ...
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ADAU1701 TYPICAL APPLICATION SCHEMATIC – SPI CONTROL Preliminary Technical Data Rev. PrF | Page ...
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Preliminary Technical Data DIGITAL TIMING DIAGRAMS t BIH BCLK_IN t BIL t LIS LRCLK_IN t SIS SDATA_INX LEFT-JUSTIFIED MSB MODE t SDATA_INX 2 I S-JUSTIFIED MODE SDATA_INX RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT ...
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ADAU1701 t CLS CLATCH CCLK CDATA t CDS COUT SDA SCLK t MCLK RESETB t CCPL t CCPH t CDH Figure 39. SPI Port Timing TSCH SCLH SCS SCLL ST 2 ...
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... PLANE ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 ADAU1701JSTZ 0°C to 70°C ADAU1701JSTZ-RL 0°C to 70°C EVAL-ADAU1701EB Pb-free ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05797-0-5/06(PrF) 0.75 1.60 0.60 MAX 0.45 SEATING PLANE 10° ...