EVAL-AD5680EB AD [Analog Devices], EVAL-AD5680EB Datasheet - Page 4

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EVAL-AD5680EB

Manufacturer Part Number
EVAL-AD5680EB
Description
5 V 18-Bit nanoDAC in a SOT-23
Manufacturer
AD [Analog Devices]
Datasheet
AD5680
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
1
1
2
3
4
5
6
7
8
9
10
Maximum SCLK frequency is 30 MHz at V
DD
1
= 4.5 V to 5.5 V; all specifications T
SYNC
SCLK
DIN
Limit at T
V
33
13
13
13
5
4.5
0
33
13
0
DD
= 4.5 V to 5.5 V
t
MIN
8
t
10
DD
, T
= 4.5 V to 5.5 V.
MAX
DB23
MIN
t
4
to T
t
5
t
6
MAX
, unless otherwise noted.
t
3
Figure 2. Serial Write Operation
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
1
Rev. 0 | Page 4 of 20
t
2
DB0
DD
t
7
) and timed from a voltage level of (V
t
9
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
IL
+ V
IH
)/2. See Figure 2.

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