EVAL-AD5680EB AD [Analog Devices], EVAL-AD5680EB Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD5680EB
• Description: 5 V 18-Bit nanoDAC in a SOT-23
• Manufacturer: AD [Analog Devices]

AD5680
SERIAL INTERFACE
The AD5680 has a 3-wire serial interface ( SYNC , SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as with most DSPs. See Figure 2 for
a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5680 compatible with high speed
DSPs. On the 24
in and the programmed function is executed, that is, a change
in DAC register contents occurs. At this stage, the SYNC line
can be kept low or be brought high. In either case, it must be
brought high for a minimum of 33 ns before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. Because the SYNC buffer draws more current
when V
idled low between write sequences for even lower power
operation. As mentioned previously it must, however, be
brought high again just before the next write sequence.
DB23 (MSB)
X
SYNC
SCLK
IN
DIN
X
= 2 V than it does when V
X
th
SYNC HIGH BEFORE 24
falling clock edge, the last data bit is clocked
X
DB23
INVALID WRITE SEQUENCE:
D17
D16
D15
TH
IN
FALLING EDGE
= 0.8 V, SYNC should be
D14
DB0
D13
D12
Figure 25. Input Register Contents
Figure 26. SYNC Interrupt Facility
D11
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D10
DATA BITS
D9
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 25). The first
four bits are don’t care bits. The next 18 bits are the data bits
followed by two don’t care bits. These are transferred to the
DAC register on the 24
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24
24
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 26).
POWER-ON RESET
The AD5680 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5680-1
DAC output powers up to 0 V, and the AD5680-2 DAC output
powers up to midscale. The output remains there until a valid
write sequence is made to the DAC. This is useful in
applications where it is important to know the output state of
the DAC while it is in the process of powering up.
D8
th
th
falling edge. However, if SYNC is brought high before the
falling edge, this acts as an interrupt to the write sequence.
VALID WRITE SEQUENCE, OUTPUT UPDATES
D7
DB23
D6
ON THE 24
D5
TH
FALLING EDGE
th
D4
falling edge of SCLK.
D3
DB0
D2
D1
D0
X
DB0 (LSB)
X