ADIS16136/PCBZ AD [Analog Devices], ADIS16136/PCBZ Datasheet - Page 8

• Manufacturer Part Number: ADIS16136/PCBZ
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The
initialization. As soon as it has a valid power supply, it initializes
and starts sampling, processing, and loading sensor data into
the output registers. After each sample cycle concludes, DIO1
pulses high. The SPI interface enables simple integration with
many embedded processor platforms, as shown in Figure 10
(electrical connection) and Table 6 (processor pin names and
functions).
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ
MOSI
MISO
SCLK
The
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 13. Table 7 provides a list of
the most common settings that require attention to initialize a
processor serial port for the
ADIS16136
ADIS16136
ADIS16136
SYSTEM
PROCESSOR
SPI MASTER
VDD
DOUT
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH-IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
SCLK
Figure 10. Electrical Connection Diagram
DIN
FOR OTHER DEVICES.
CS
is an autonomous system that requires no user
SPI interface supports full duplex serial
I/O LINES ARE COMPATIBLE WITH
SCLK
MOSI
MISO
3.3V OR 5V LOGIC LEVELS
IRQ
Function
Slave select
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
SS
D15
R/W
ADIS16136
D14
A6
D13
A5
6
3
5
4
7
CS
SCLK
DIN
DOUT
DIO1
D12
A4
SPI interface.
10
13
D11
A3
ADIS16136
5V
11
14
D10
A2
Figure 13. SPI Communication Bit Sequence
12
15
A1
D9
A0
D8
Rev. A | Page 8 of 20
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D7
D6
D5
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
READING SENSOR DATA
A single register read requires two 16-bit SPI cycles. The first
cycle requests the contents of a register using the bit assignments
in Figure 13. Then, the register contents follow on DOUT during
the second sequence. Figure 11 includes three single register reads
in succession. In this example, the process starts with Pin 5,
DIN = 0x0600, to request the contents of the GYRO_OUT
register and follows with 0x0400 to request the contents of the
GYRO_OUT2 register and with 0x0200 to request the contents
of the TEMP_OUT register. Full duplex operation enables pro-
cessors to use the same 16-bit SPI cycle to read data from DOUT
while requesting the next set of data on the DIN pin. Figure 12
provides an example of the four SPI signals when reading
GYRO_OUT in a repeating pattern.
DOUT
DIN
DOUT
DOUT = 1111 1001 1101 1010 = 0xF9DA = –1574 LSBs = –29.765°/sec
D4
SCLK
DIN
CS
D3
Figure 12. SPI Read Example, Second 16-Bit Sequence
0x0600
D2
D1
Figure 11. SPI Read Example
Description
ADIS16136
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence
Shift register/data length
GYRO_OUT
D0
0x0400
DIN = 0000 0110 0000 0000 = 0x0600
operates as a slave
D15
GYRO_OUT2
R/W
0x0200
D14
A6
D13
A5
Data Sheet
TEMP_OUT