ADIS16136/PCBZ AD [Analog Devices], ADIS16136/PCBZ Datasheet - Page 4

• Manufacturer Part Number: ADIS16136/PCBZ
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
T
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
Timing Diagrams
ADIS16136
SCLK
STALL
READRATE
CS
DAV
DSU
DHD
SCLKR
DR
SFS
1
2
3
x
Guaranteed by design and characterization but not tested in production.
A
, t
= 25°C, VDD = 5 V, unless otherwise noted.
DF
, t
SCLKF
DOUT
SCLK
DIN
CS
SCLK
CS
Description
Serial clock
Stall period between data, see Figure 3
Read rate
Chip select to clock edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise and fall times
DOUT rise and fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync to data ready output
Input sync period
Input sync low time
t
CS
1
MSB
R/W
CLOCK (CLKIN)
2
A6
READY
SYNC
DB14
t
DATA
DAV
t
DSU
3
A5
DB13
t
1
Figure 4. Input Clock Timing Diagram
Figure 2. SPI Timing and Sequence
Figure 3. Stall Time and Data Rate
4
t
DHD
t
A4
READRATE
DB12
Rev. A | Page 4 of 20
t
3
t
X
t
5
STALL
A3
DB11
6
A2
DB10
t
2
Min
0.01
15
25
48.8
24.4
48.8
0
5
488
100
1
D2
DB2
15
Normal Mode
Typ
5
5
300
D1
DB1
16
LSB
LSB
Max
2.5
25
12.5
12.5
t
SFS
Data Sheet
Unit
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs