LC89515 Sanyo, LC89515 Datasheet - Page 4

• Manufacturer Part Number: LC89515
• Description: CD-ROM/CD-I Error Correction/ Host Interface LSI
• Manufacturer: Sanyo

4. Points Common to All Blocks
5. Register Table
Read
Note: The values of the shaded bits are ignored.
RS
0
1
Furthermore, the LC89515K SELDRQ pin can be used to perform DRQ (data request) transfers. This is a technique
in which transfers are performed by the host outputting HRD pulses according to a data request signal output from
the LC89515K and is similar to DMA controller operation.
When the last byte of the count specified by the control microprocessor is read, EOP goes active while the read pulse
is output. Also DTEN is set inactive after this time. Next, a transfer complete interrupt is issued to inform the control
microprocessor that the transfer to the host has completed.
The LC89515K control microprocessor can pass the decoding result for the data requested by the host and the CD-
ROM drive status information to the host by writing to the LC89515K internal status registers. The status registers
are a 12-byte FIFO, and the host reads out data while the STEN signal is low. The STEN signal goes high when the
last byte is read. The LC89515K has nothing to do with the content of the status registers.
Since the command and status registers are neither interpreted nor executed by the LC89515K, the LC89515K user
can define the command and status data as unrestricted protocols between the host and the microprocessor. This
allows CD-ROM application systems to be designed without restriction, and also allows an existing system to be
replaced by a system using the LC89515K.
The LC89515K performs data input and decoding at the same time in a pipelined manner. Also, writes of input data
to the buffer RAM, writes of data to be decoded, and reads to the buffer RAM for transfers to the host all proceed at
the same time with synchronization always being maintained by the LC89515K. Therefore there is no need for the
control microprocessor to be concerned with which master (system block) is accessing the buffer RAM.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AR
—
R10
R11
R12
R13
R14
R15
No.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
—
IFSTAT
Symbol
COMIN
HEAD0
HEAD1
HEAD2
HEAD3
STAT0
STAT1
STAT2
STAT3
DBCH
DBCL
WAH
WAL
PTH
PTL
AR
MINERA
RMOD3
CRCOK
VALST
CMDI
DTEI
BIT7
msb
msb
msb
msb
msb
A
A
B
A
A
0
15
15
7
7
7
SECERA
WLONG
ILSYNC
RMOD2
DTEI
DTEI
BIT6
A
A
B
A
A
—
—
—
—
—
0
14
14
6
6
6
NOSYNC
BLKERA
RMOD1
LC89515K
CBLK
DECI
DTEI
BIT5
A
A
—
B
—
—
—
—
A
A
0
13
13
5
5
5
MODERA
RMOD0
LBLK
DTEI
BIT4
A
A
B
A
A
—
—
—
—
—
0
1
12
12
4
4
4
WSHORT
SH0ERA
DTBSY
MODE
BIT3
B
A
A
A
—
B
—
—
—
—
A
A
11
11
11
3
3
3
3
SH1ERA
NOCOR
STBSY
SBLK
BIT2
B
A
A
A
B
A
A
—
—
—
—
—
10
10
10
2
2
2
2
RFORM1
ERABLK
SH2ERA
DTEN
BIT1
A
B
B
A
A
A
A
—
—
—
—
—
1
1
9
1
9
1
9
No. 4272-4/6
RFORM0
UCEBLK
SH3ERA
STEN
BIT0
lsb
lsb
lsb
lsb
lsb
A
B
B
A
A
A
A
0
0
8
0
8
0
8