LC74799 Sanyo Semiconductor Corporation, LC74799 Datasheet
LC74799
Related parts for LC74799
LC74799 Summary of contents
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... Ordering number : EN5834 Overview The LC74799 and LC74799M are on-screen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs include a built-in PDC/VPS/UDT interface circuit. Features • Display format: 24 characters by 12 rows (Up to 288 characters) • ...
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... Pin Assignment LC74799, 74799M No. 5834-2/32 ...
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... Power supply (+ Note *: A capacitor of at least 2000 pF must be connected between the V LC74799, 74799M Notes Ground connection (digital system ground) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals input an external clock signal (2fsc or 4fsc) ...
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... OL Three-value output voltage Input current Operating mode current drain SYNC level V SN Pedestal level V PD Color burst low level V CBL LC74799, 74799M Symbol Conditions V max V 1 and All input pins SEP , SYNC OUT OUT OUT JDG Pd max Ta = 25°C Topr Tstg ...
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... BUF Start hold time STA SCL low-level period t LOW SCL high-level period t HIGH Data hold time DAT Data setup time DAT Rise time t R Fall time t F Stop setup time STO LC74799, 74799M Conditions ( 5.0 V, OUT (3) ( 5.0 V, OUT (3) (1) ...
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... Figure 1 OSD Serial Data Input Timing S: Start condition P: Stop condition Note: DOUT goes to the high-impedance state while CS2 is high. Figure 2 PDC/VPS Serial Timing (I LC74799, 74799M 2 C bus) No. 5834-6/32 ...
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... System Block Diagram Decoder LC74799, 74799M No. 5834-7/32 ...
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... Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74799/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74799/M is set to the COMMAND0 (display memory write address setup mode) state. LC74799, 74799M ...
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... Display memory column address ( hexadecimal Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. COMMAND1 (Display character data write setup command) • First byte DA Register State 7 — — 0 Command 1 identification code. Sets up display character data write mode. ...
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... Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. COMMAND2 (Vertical display start position and vertical character size setup command) • First byte DA Register State 7 — — 0 Command 2 identification code. Sets the vertical display start position and the vertical character size. ...
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... HP3 ( 1 2 ∑ n HP2 1 Tc: Period of the oscillator in operating mode HP1 1 HP0 0 0 (LSB) 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function HS20 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot HS10 1Tc/dot 2Tc/dot 1 3Tc/dot 1Tc/dot ...
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... Reverse video off Reverse video on 0 Character display off 0 DSPON 1 Character display on Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function BLK0 0 1 Blanking off Character size Frame size Complete fill in size ...
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... CB 1 Color burst signal output stopped 0 PH2 2 PH2 PH1 PH0 1 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function PH1 PH0 Background color (phase Cyan Yellow Red Blue Cyan blue ...
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... SN2 SN1 SN0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function MOD0 DAV Sliced data width 1 CSYNC ST.PULSE is held at the pedestal level OUT Contents Function RN0 Number of times HSYNC detected 0 32 times ...
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... MSKERS 1 Mask invalid 0 3H (NTSC) 1 MSKSEL 1 20H (NTSC) 0 Frame level 0 only (V 0 EGL 1 Two-stage frame level (V Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function ) BK0 and V ) BK0 BK1 Notes Notes CV ...
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... LNA0 LPA2 2 LPA2 LPA1 LNA0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function Specified line not change the line background 0 1 Line Line Line Line Line Line Line Line Line 9 ...
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... LNB0 LPB2 2 LPB2 LPB1 LNB0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function Specified line not change the line background 0 1 Line Line Line Line Line Line Line Line Line 9 ...
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... LNC0 LPC2 2 LPC2 LPC1 LNC0 1 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function Specified line not change the line background 0 1 Line Line Line Line Line Line Line Line Line 9 ...
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... The LNBSEL = 1 setting specifications RV characters have the background color specified by PH* and 0 MOD2 1 characters are white Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function Notes Notes ...
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... Vertical synchronization signal input (external synchronization) 1 SEL1 1 Frame signal input 0 Internal V separation used 0 CTL3 1 Internal V separation not used (external V separation) Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function pin IN SEL2 HLFTOM Output ...
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... VPM2 VPM1 VPM0 Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function CPA1 CPA0 Clock No.1 Operating mode 0 0 VPS 0 1 8/30/2 (PDC Automatic PDC/VPS switching 1 1 8/30/1 (UDT) ...
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... VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1: 1 bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21, status 1 (3): bytes 7 to 25, status 2 (4): bytes Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function ...
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... Byte 11 biphase error check off (Data write) 0 Byte 5 biphase error check on (Data hold) 0 ECV5 1 Byte 5 biphase error check off (Data write) Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function 2 C bus ...
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... Byte 13 Hamming error check on (Data hold) 0 {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} 0 ECP13 Byte 13 Hamming error check off (Data write) 1 {Bytes 38, 22, 30, 14, 26, 36, 26, and 36} Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function 2 C bus ...
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... Byte 20 Hamming error check on (Data hold) 0 {Bytes 45, 29, 37, 21, 33, 43, 33, and 43} 0 ECP20 Byte 20 Hamming error check off (Data write) 1 {Bytes 45, 29, 37, 21, 33, 43, 33, and 43} Note: All registers are set to 0 when the LC74799/M is reset by the RST pin. LC74799, 74799M Contents Function Contents Function 2 C bus ...
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... Byte 5 Bit 7 byte 19 bit Byte 6 Bit 7 byte 20 bit LC74799, 74799M PDC 8/30 mode VPS mode Format 2 byte 16 bit 0 byte byte 17 bit byte 18 bit 0 byte byte 19 bit byte 20 bit 0 byte byte 21 bit byte 22 bit 0 byte byte 23 bit byte 14 bit 0 byte 5 1 ...
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... Byte 12 Bit 7 byte 24 bit Byte 13 Bit 7 byte 25 bit Bits for which data is not set are set to 1. LC74799, 74799M PDC 8/30 mode VPS mode Format 2 byte 13 bit Error byte 16 Error information 1 17 information Error 14 information Header time mode 1 (3) Header time mode 2 (4) ...
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... Byte 5 Bit 7 byte 30 bit 0 6 (30 Byte 6 Bit 7 byte 31 bit 0 6 (31 Byte 7 Bit 7 byte 32 bit 0 6 (32 LC74799, 74799M 8/30 8/30/1 Status display PAL Puls mode 2 (4) byte 36 bit 0 bit 0 (36 byte 37 bit 0 bit 8 (37 byte 38 bit 0 (38 byte 39 bit 0 (39 byte 40 bit 0 ...
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... Byte 12 Bit 7 Error byte 34 (34) 6 information 2 35 (35 Byte 13 Bit Bits for which data is not set are set to 1. LC74799, 74799M Status display PAL Puls mode 2 (4) byte 43 bit 0 (43 byte 44 bit 0 (44 byte 45 bit 0 (45 Error byte 36 (36) ...
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... Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row ( hexadecimal) and column ( hexadecimal) addresses. Display Screen Structure (display memory addresses) 12 Rows LC74799, 74799M 24 Characters No. 5834-30/32 ...
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... Frame Pedestal Color burst low CBL V : Sync SN Note 5.00V. The values in parentheses for V DD LC74799, 74799M 2 = 5.00 V) Output voltage (1) [V] 2.65 2.37 (2.01) 1.67 1.23 (1.16) 2.08 1.50 1.37 1.07 0.80 and V are the values for a blue background. RSH RSL Output voltage (2) [V] Output voltage (3) [V] 2 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. LC74799, 74799M PS No. 5834-32/32 ...