LC8901Q Sanyo, LC8901Q Datasheet
LC8901Q
Related parts for LC8901Q
LC8901Q Summary of contents
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... Ordering number : EN4079B Overview The LC8901 and LC8901Q are LSIs for use in IEC958, EIAJ CP-1201 format data transmission between digital audio equipment. These LSIs are used on the receiving side, and handle synchronization with the input signal and demodulation of that signal to a normal format signal. ...
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... Usage overview diagram Assumes the use of both digital and analog source modes. Digital source mode Analog source mode Pin Assignment LC8901 (DIP42S) LC8901, 8901Q LC8901Q (QIP44M) No. 4079-2/15 ...
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Block Diagram LC8901, 8901Q No. 4079-3/15 ...
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Pin Functions LC8901 (DIP42S) Pin No. Symbol I/O 1 DIN1 I 2 DIN2 I Data input pins with built-in amplifiers 3 DIN3 I 4 DIN4 I 5 DGND — Digital system ground 6 DIN5 I Data input pins without built-in ...
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... LC8901Q (QIP44M) Pin No. Symbol I/O 1 DIN5 I Data input pins without built-in amplifiers 2 DIN6 I 3 DOUT1 O Input data through output 4 DOUT2 O 5 RC1 I RC oscillator connection 6 RC2 O 7 LPF I High: LPF time constant switching mode, low: fixed mode. This pin is normally high. 8 STOP ...
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Specifications Absolute Maximum Ratings 25°C Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Operating temperature Storage temperature Allowable Operating Ranges Parameter Symbol Supply voltage V DD Operating temperature Topr DC Characteristics –30 ...
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Waveforms for the AC Characteristics Microprocessor Interface Block AC Characteristics –30 to +75°C, V Parameter Symbol CL low-level pulse width TWL CL high-level pulse Width TWH Data setup time TDS Data hold time TDH CL rise time ...
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... Waveforms for the Microprocessor Interface Block Input mode Output mode Clock Modes The LC8901 and LC8901Q support 4 clock modes selected by the XSYS and CLK pins. XSYS pin CLK pin L L The system clock is 384fs synchronized to the input data, which is then demodulated. ...
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LPF Pin Setting the LPF pin high sets the PLL low-pass filter time constant to a mode in which it is automatically switched by the PLL locking state. This pin should be set high normally. Microprocessor Interface The data input ...
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Microprocessor Interface Input 1. Input pin setting The data input pins DIN1 to DIN4 have built-in amplifiers and can receive signals from a minimum amplitude of 400 mVp maximum amplitude of V only for use with optical inputs. ...
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Microprocessor Interface Output The table lists the content of the bits D0 to D15 in the microprocessor interface format. Bit D0 Invalid bit. A low level is always output. D1 Indicate the sampling frequency. D2 Correspond to the 2 external ...
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PLL 1. The VCO is formed from a ring oscillator. 2. PLL operation starts when correct data is input to the data demodulation system and the XMODE pin goes high. 3. The low-pass filter time constant can be automatically switched ...
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Data Output Timing The figure below shows the data output timing. 1. Data is output in synchronization with the falling edge of the BCLK signal. 2. Data, BCLK, and LRCK are output in synchronization with the rising edge of the ...
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Sample Application Circuit Note: All input pin resistors and capacitors are the same. Recommended Constants for the Application Circuit Item Symbol Constant value R1 330 kΩ kΩ kΩ R4 5.1 kΩ Resistors R5 5.1 kΩ 150 ...
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... Information (including circuit diagrams and circuit parameters) herein is for example only not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ...