UPD65MC NEC, UPD65MC Datasheet
UPD65MC
Available stocks
Related parts for UPD65MC
UPD65MC Summary of contents
Page 1
... Unless otherwise specified, the PD65 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14380EJ2V0DS00 (2nd edition) ...
Page 2
ORDERING INFORMATION Part Number PD64AMC- -5A4 20-pin plastic SSOP (300 mil) PD65MC- -5A4 20-pin plastic SSOP (300 mil) Remark indicates ROM code suffix. PIN CONFIGURATION (TOP VIEW) 20-pin Plastic SSOP (300 mil) • PD64AMC- -5A4 • PD65MC- -5A4 K I/O6 ...
Page 3
BLOCK DIAGRAM CARRIER REM GENERATOR 9-bit S /LED 1 TIMER LIST OF FUNCTIONS Item ROM capacity 1002 Mask ROM RAM capacity 32 4 bits Stack 1 level (multiplexed with RF of RAM) I/O pins • Key input (K • Key ...
Page 4
PIN FUNCTIONS ............................................................................................................................... 1.1 List of Pin Functions ............................................................................................................................... 1.2 INPUT/OUTPUT Circuits of Pins ............................................................................................................ 1.3 Dealing with Unused Pins ...................................................................................................................... 2. INTERNAL CPU FUNCTIONS .......................................................................................................... 2.1 Program Counter (PC) ............................................................................................................................ 2.2 Stack Pointer (SP) ................................................................................................................................... 2.3 Address Stack ...
Page 5
INSTRUCTION SET .......................................................................................................................... 30 9.1 Machine Language Output by Assembler ............................................................................................. 30 9.2 Circuit Symbol Description .................................................................................................................... 31 9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ..................................... 32 9.4 Accumulator Operation Instructions ..................................................................................................... 36 9.5 Input/Output Instructions ....................................................................................................................... ...
Page 6
... When the STOP mode release is disabled, this pin can be used as the input port which does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) Note 2 These pins refer to the 4-bit input ports. 11-14 ...
Page 7
INPUT/OUTPUT Circuits of Pins The input/output circuits of the PD64A and 65 pins are shown in partially simplified forms below. ( I/O0 I/O7 Output data latch output disable Input buffer Note The drive capability is held low. ...
Page 8
... Dealing with Unused Pins The following connections are recommended for unused pins. Table 1-1. Connections for Unused Pins Pin K INPUT mode I/O OUTPUT mode REM S /LED Caution The I/O mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program. ...
Page 9
INTERNAL CPU FUNCTIONS 2.1 Program Counter (PC): 11 Bits Refers to the binary counter that holds the address information of the program memory. Figure 2-1. Program Counter Organization PC PC10 PC9 PC8 The program counter contains the address of ...
Page 10
Program Memory (ROM): 1002 steps 2026 steps The ROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from 7EAH to 7FFH cannot ...
Page 11
Figure 2-4. Data Memory Organization R (high-order 4 bits ...
Page 12
Arithmetic and Logic Unit (ALU): 4 Bits The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple manipulations with priority given to logical operations. 2.9 Flags 2.9.1 Status flag (F) Pin ...
Page 13
Carry flag (CY) The carry flag is set ( the following cases: • If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is “1” and bit 3 of the operand ...
Page 14
PORT REGISTERS (PX) The K port, the K port, the special ports (S I reset, port register values are shown below. Figure 3-1. Port Register Organization I/O7 I/O6 I/ ...
Page 15
... Caution During double pressing of a key, a high-level output and a low-level output may coincide with each other at the K port. To avoid this, the low-level output current of the K I/O low. Therefore, be careful when using the K The K port is so designed that, even when connected directly to V I/O voltage range (V = 2.0 to 3.6 V), no problem may occur. DD Bit ...
Page 16
... When in INPUT mode, software can be used to set the availability of the pull-down resistor of the S S /LED ports in 2-bit units by means of bit 4 of the P4 register. 1 When in OUTPUT mode, the pull-down resistor is automatically disconnected thus becoming the remote control transmission display pin (refer to 4. TIMER). When reset placed in OUTPUT mode, and high level is output. 16 ...
Page 17
... When using the pin as a key input from a key matrix, enable (bit register is set to 1) the use of the STOP mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled (bit register is set to 0), it can be used as the input port which does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally ...
Page 18
... Specifies the availability of the pull-down resistor “1” (available Specifies the availability of the pull-down resistor “1” (available). Remark In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected ...
Page 19
TIMER 4.1 Timer Configuration The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter ( flag ( ...
Page 20
Timer Operation The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation instruction. The timer operation instructions for making the timer start operation are shown below: MOV T0, ...
Page 21
Carrier Output The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of the control register 0. As shown in Figure 4-3, in the case where the timer stops when the ...
Page 22
STANDBY FUNCTION 5.1 Outline of Standby Function To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, are made available. In STOP mode, the system clock stops oscillation. At this time, the X In ...
Page 23
Standby Mode Setup and Release The standby mode is set with the HALT #b standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release ...
Page 24
Table 5-3. Standby Mode Setup (HALT #b Operand Value of HALT Instruction Setting Mode STOP STOP Note STOP 1 Any of ...
Page 25
... At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode necessary to hold the release condition longer than the wait time. (2) HALT Mode Release Timing Figure 5-2 ...
Page 26
RESET The system reset takes effect by means of the causes as follows: • When the POC circuit has detected low-power voltage • When the operand value is illegal or does not satisfy the precondition when the HALT instruction ...
Page 27
POC CIRCUIT The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller at the time of battery replacement. Cautions 1. There are cases in which the POC circuit cannot detect a low power ...
Page 28
... POC-detected voltage). Whether this condition is being met or not can be checked by measuring the oscillation status on a product which actually contains a POC circuit, as follows. <1> Connect a storage oscilloscope to the X <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage V from 0 V (making sure to avoid V ...
Page 29
SYSTEM CLOCK OSCILLATOR The system clock oscillator consists of oscillators for ceramic resonators (f Ceramic resonator The system clock oscillator stops its oscillation when reset or in STOP mode. Caution When using the system clock oscillator, wire area indicated ...
Page 30
INSTRUCTION SET 9.1 Machine Language Output by Assembler The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per ...
Page 31
Circuit Symbol Description A : Accumulator ASR : Address Stack Register addr : Program memory address CY : Carry flag data4 : 4-bit immediate data data8 : 8-bit immediate data data10 : 10-bit immediate data F : Status flag ...
Page 32
Mnemonic to/from Machine Language (Assembler Output) Contrast Table Accumulator Operation Instructions Instruction Code Mnemonic Operand 1st Word 2nd Word ANL A, R0n FBEn A, R1n FAEn A, @R0H FAF0 A, @R0L FBF0 A, #data4 FBF1 data4 ORL A, R0n ...
Page 33
Input/output Instructions Instruction Code Mnemonic Operand 1st Word 2nd Word IN A, P0n FFF8 + n — A, P1n FEF8 + n — OUT P0n, A E5F8 + n — P1n, A E4F8 + n — ANL A, P0n FBF8 ...
Page 34
Branch Instructions Instruction Code Mnemonic Operand 1st Word 2nd Word JMP addr (Page 0) E8F1 addr addr (Page 1) E9F1 addr JC addr (Page 0) ECF1 addr addr (Page 1) EAF1 addr JNC addr (Page 0) EDF1 addr addr (Page ...
Page 35
Others Instruction Code Mnemonic Operand 1st Word 2nd Word HALT #data4 E2F1 data4 STTS #data4 E3F1 data4 R0n E3En SCAF FAF3 NOP E0E0 Operation 3rd Word Standby mode if statuses match F 1 else statuses match F ...
Page 36
Accumulator Operation Instructions ANL A, R0n ANL A, R1n <1> Instruction code : <2> Cycle count : 1 <3> Function : (A) CY The accumulator contents and the register Rmn contents are ANDed and ...
Page 37
ORL A, R0n ORL A, R1n <1> Instruction code : <2> Cycle count : 1 <3> Function : (A) ( The accumulator contents and the register Rmn contents are ORed and the results ...
Page 38
XRL A, @R0H XRL A, @R0L <1> Instruction code : 0 <2> Cycle count : 1 <3> Function : (A) CY (A) CY The accumulator contents and the program memory contents ...
Page 39
Input/Output Instructions IN A, P0n IN A, P1n <1> Instruction code : <2> Cycle count : 1 <3> Function : (A) (Pmn ...
Page 40
OUT Pn, #data8 <1> Instruction code : <2> Cycle count : 1 <3> Function : (Pn) The immediate data is transferred to port Pn. In this ...
Page 41
MOV R0n, A MOV R1n, A <1> Instruction code : <2> Cycle count : 1 <3> Function : (Rmn) The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code : 0 ...
Page 42
... Branch Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization unnecessary to designate pages. The pages allowed for each product are as follows. PD64A (ROM: 1K steps) : page 0 PD65 (ROM: 2K steps) : pages 0, 1 PD6P5 (PROM: 2K steps) : pages 0, 1 JMP addr < ...
Page 43
... Subroutine Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization unnecessary to designate pages. The pages allowed for each product are as follows. PD64A (ROM: 1K steps) : page 0 PD65 (ROM: 2K steps) : pages 0, 1 PD6P5 (PROM: 2K steps) : pages 0, 1 CALL addr < ...
Page 44
Timer Operation Instructions MOV A, T0 MOV A, T1 <1> Instruction code : 0 <2> Cycle count : 1 <3> Function : (A) CY The timer Tn contents are transferred ...
Page 45
MOV T, @R0 <1> Instruction code : <2> Cycle count : 1 <3> Function : (T) ((P13), (R0)) Transfers the program memory contents to the timer register T (t P13 ...
Page 46
STTS #data4 <1> Instruction code : <2> Cycle count : 1 <3> Function : if statuses match F else F Compares the ...
Page 47
... ASSEMBLER RESERVED WORDS 10.1 Mask Option Directives When creating the PD64A and 65 program necessary to use a mask option directive in the assembler’s source program. 10.1.1 OPTION and ENDOP directives From the OPTION directive on to the ENDOP directive are called the mask option definition block. The format ...
Page 48
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Power supply voltage V DD Input voltage I/O Output voltage V O Note High-level output current I REM OH LED One K Total of ...
Page 49
DC Characteristics (T = – Parameter Symbol High-level input voltage V S IH1 IH2 I IH3 I Low-level input voltage V S IL1 IL2 I/O ...
Page 50
AC Characteristics (T = – Parameter Symbol Command execution time high-level width When releasing STANDBY mode Note 10 + 52/f ...
Page 51
... Unnecessary (C-containing type) 3. Unnecessary (C-containing type) 3. Unnecessary (C-containing type) 3. Unnecessary (C-containing type) 3. Unnecessary (C-containing type) 4 Unnecessary (C-containing type) 6 Unnecessary (C-containing type) 8 Unnecessary (C-containing type OUT C1 C2 Data Sheet U14380EJ2V0DS00 PD64A, 65 Remark MAX. 3.6 51 ...
Page 52
CHARACTERISTIC CURVE (REFERENCE VALUES ( MHz 0.9 0.8 0.7 0.6 OPERATING mode 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 Power supply voltage (REM, LED) ...
Page 53
APPLIED CIRCUIT EXAMPLE Example of Application to System · Remote-control transmitter (48 keys; mode selection switch accommodated) K I/ /LED 1 REM OUT X IN GND Note S 2 ...
Page 54
PACKAGE DRAWINGS 20 PIN PLASTIC SSOP (300 mil NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. Remark The dimensions and materials of ...
Page 55
... Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult one of our NEC sales representatives. Table 15-1. Soldering Conditions for Surface-Mount Type ...
Page 56
APPENDIX A. DEVELOPMENT TOOLS An emulator is provided for the PD64A and 65. Hardware Note • Emulator (EB- used to emulate the PD64A and 65. Note This is a product of Naito Densei Machida Mfg. Co., Ltd. ...
Page 57
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN PD64A, 65 AND OTHER PRODUCTS Item PD62 ROM capacity 512 10 bits RAM capacity 32 4 bits Stack 1 level (multiplexed with RF of RAM) Key matrix keys Key extended input ...
Page 58
... APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode) Caution When using the NEC transmission format, please apply for a custom code at NEC. (1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.) REM output 58.5 to 76.5 ms < ...
Page 59
... Leader code Custom code Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code’) and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present ...
Page 60
Data Sheet U14380EJ2V0DS00 PD64A, 65 ...
Page 61
Data Sheet U14380EJ2V0DS00 PD64A ...
Page 62
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 63
... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
Page 64
... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...