K4S640832D Samsung semiconductor, K4S640832D Datasheet - Page 2

• Manufacturer Part Number: K4S640832D
• Description: 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: Samsung semiconductor

2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
FUNCTIONAL BLOCK DIAGRAM
K4S640832D
clock
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
*
CLK
Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Programming Register
WE
K4S640832D-TC/L75
K4S640832D-TC/L80
K4S640832D-TC/L1H
K4S640832D-TC/L1L
K4S640832D-TC/L10 66MHz(CL=2 &3)
Data Input Register
The K4S640832D is 67,108,864 bits synchronous high data
Column Decoder
2M x 8
2M x 8
2M x 8
2M x 8
Part No.
DQM
LWCBR
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.0 May 1999
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
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