AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 171

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

6
5
4
3
2
1
0
LNKSE
RCVME
XMTE
RES
RCVE
RES
COLE
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
Read/Write accessible always.
LNKSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network that has
passed the address match func-
tion for this node. All address
matching modes are included:
physical, logical filtering, broad-
cast, and promiscuous.
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
Reserved location. Written and
read as zeros.
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network.
Reserved location. Written and
read as zeros.
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
Read/Write accessible always.
RCVME is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Read/Write accessible always.
XMTE is set to 1 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Read/Write accessible always.
RCVE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
P R E L I M I N A R Y
Am79C973/Am79C975
BCR9: Full-Duplex Control
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-3
2
1
0
RES
FDRPAD
RES
FDEN
Name
Read/Write accessible always.
COLE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Full-Duplex Runt Packet Accept
Disable. When FDRPAD is set to
1 and full-duplex mode is en-
abled,
Am79C975 controller will only re-
ceive frames that meet the mini-
mum Ethernet frame length of 64
bytes. Receive DMA will not start
until at least 64 bytes or a com-
plete frame have been received.
By default, FDRPAD is cleared to
0. The Am79C973/Am79C975
controller will accept any length
frame and receive DMA will start
according to the programming of
the receive FIFO watermark.
Note that there should not be any
runt packets in a full-duplex net-
work, since the main cause for
runt packets is a network collision
and there are no collisions in a
full-duplex
needs to be set if in full-duplex
mode and external address rejec-
tion (EAR (BCR9, bit 2)) function-
ality is desired.
Read/Write accessible always.
FDRPAD is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Full-Duplex Enable. FDEN con-
trols whether full-duplex opera-
tion is enabled. When FDEN is
cleared and the Auto-Negotiation
is disabled, full-duplex operation
is
Am79C973/Am79C975 controller
Description
not
enabled
the
network.
Am79C973/
and
This
171
the
bit