AM79C973KCW Advanced Micro Devices, AM79C973KCW Datasheet - Page 139

• Manufacturer Part Number: AM79C973KCW
• Description: PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
• Manufacturer: Advanced Micro Devices

3
2
DXMTFCS Disable Transmit CRC (FCS).
LOOP
troller must be in internal loop-
back for FCOLL to be valid. If
FCOLL = 1, a collision will be
forced during loopback transmis-
sion attempts, which will result in
a Retry Error. If FCOLL = 0, the
Force Collision logic will be dis-
abled. FCOLL is defined after the
initialization block is read.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS and ENP bits are set
in TMD1.
bit11) is set to 1, the setting of
DXMTFCS has no effect on
frames shorter than 64 bytes.
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit was called DTCR in the
LANCE (Am7990) device.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Am79C973/Am79C975 controller
to operate in full-duplex mode for
test purposes. The setting of the
full-
have no effect when the device
operates
When LOOP = 1, loopback is en-
abled. In combination with INTL
and
When APAD_XMT bit (CSR4,
Loopback Enable allows the
DXMTFCS
duplex control bits in BCR9
the
MIIILP, various loopback
in
transmitted
loopback
is
P R E L I M I N A R Y
set
Am79C973/Am79C975
frame.
mode.
and
1
0
CSR16: Initialization Block Address Lower
Bit
31-16 RES
15-0
LOOP
0
0
1
DTX
DRX
Name
IADRL
Table 24. Loopback Configuration
INTL
0
0
0
MIIILP
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
modes are defined as follows in
Table 24.
Am79C973/Am79C975 controller
not accessing the Transmit De-
scriptor Ring and, therefore, no
transmissions
DTX = 0, will set TXON bit (CSR0
bit 4) if STRT (CSR0 bit 1) is as-
serted.
Disable Receiver results in the
Am79C973/Am79C975 controller
not accessing the Receive De-
scriptor Ring and, therefore, all
receive frame data are ignored.
DRX = 0, will set RXON bit
(CSR0 bit 5) if STRT (CSR0 bit 1)
is asserted.
Description
Reserved locations. Written as
zeros and read as undefined.
This register is an alias of CSR1.
Disable
Refer to Loop Back Operation
section for more details.
Read/Wr ite acc essible only
when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
0
1
0
Normal Operation
Internal Loop
External Loop
Transmit
Function
are
results
attempted.
139
in