AM79C32A Advanced Micro Devices, AM79C32A Datasheet - Page 43

• Manufacturer Part Number: AM79C32A
• Description: Digital Subscriber Controller (DSC) Circuit
• Manufacturer: Advanced Micro Devices

D-Channel Mode Register 2 — (DMR2) — Read/Write
Address = Indirect 87H
DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is con-
trolled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40.
D-Channel Mode Register 3 — (DMR3) — Read/Write
Address = Indirect 8EH
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Logical 1
Enable Receive Abort interrupt (see DER bit 0)
Enable Non-integer Number of Bytes Received interrupt (see DER bit 1)
Enable Collision Abort Detected interrupt (see DER bit 2)
Enable FCS Error interrupt (see DER bit 3)
Enable Overflow Error interrupt (see DER bit 4)
Enable Underflow Error interrupt (see DER bit 5)
Enable Overrun Error interrupt (see DER bit 6)
Enable Underrun Error interrupt (see DER bit 7)
Logical 1
Enable Valid Address/End of Address interrupt (default value) (see DSR1 bit 0) Disable interrupt
Enable End of Valid Transmit Packet interrupt (default value) (see DSR1 bit 6) Disable interrupt
Enable Last Byte of Received Packet interrupt (see DSR2 bit 0)
Enable Receive Byte Available interrupt (see DSR2 bit 1)
Enable Last Byte Transmitted interrupt (see DSR2 bit 3)
Enable Transmit buffer Available interrupt (see DSR2 bit 4)
Enable Received Packet Lost interrupt (see DSR2 bit 2)
Enable FCS transfer to FIFO
Table 40. D-Channel Mode Register 2
Table 41. D-Channel Mode Register 3
Am79C30A/32A Data Sheet
Logical 0 (Default Value)
Disable interrupt (default value)
Disable interrupt (default value)
Disable interrupt (default value)
Disable interrupt (default value)
Disable interrupt (default value)
Disable FCS transfer to FIFO
(default value)
Logical 0 (Default Value)
Disable interrupt
Disable interrupt
Disable interrupt
Disable interrupt
Disable interrupt
Disable interrupt
Disable interrupt
Disable interrupt
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