AM79C32A Advanced Micro Devices, AM79C32A Datasheet - Page 12

• Manufacturer Part Number: AM79C32A
• Description: Digital Subscriber Controller (DSC) Circuit
• Manufacturer: Advanced Micro Devices

12
Bit
0
1
2
3
4
5
6
7
Interrupt Generated/Action Required
D-channel transmit threshold interrupt/load D-channel Transmit buffer
D-channel receive threshold interrupt/read D-channel Receive buffer
D-channel status interrupt/read DSR1
Source
DSR1 bit 0
DSR1 bit 1
DSR1 bit 6
D-channel error interrupt/read DER and DSR2 bit 2
Source
DER bit 1
DER bit 2
DER bit 3
DER bit 5
DER bit 6
DER bit 7
DSR2 bit 2
Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers
LIU status interrupt/read LSR
Source
LSR bit 3
LSR bit 4
LSR bit 5
LSR bit 7
D-channel status interrupt/read DSR2
Source
DSR2 bit 0
DSR2 bit 1
DSR2 bit 3
DSR2 bit 4
DSR2 bit 7
Multiframe or PP interrupt/read MFSB and PPSR
Source
MFSB bit 5
MFSB bit 6
MFSB bit 7
PPSR bit 0
PPSR bit 1
PPSR bit 2
PPSR bit 3
PPSR bit 4
PPSR bit 5
PPSR bit 6
DER bit 0
DER bit 4
Cause
Valid Address (VA) or End of Address (EOA)
When a closing flag is received or a receive error occurs
When a closing flag is transmitted DMR3 bit 1
Cause
Current received packet has been aborted
Non-integer number of bytes received
Collision abort detected
FCS error
Overflow error
Underflow error
Overrun error
Underrun error
Receive packet lost
Cause
Change of state to F3
Change of state from/to F7
Change of state from/to F8
HSW change of state
Cause
Last byte of received packet
Receive byte available
Last byte transmitted
Transmit buffer available
Start of second packet
Cause
S-data available
Q-bit buffer empty
Multiframe change of state (in/out of sync)
Monitor receive, data available
Monitor transmit, buffer available
Monitor EOM received
Monitor abort received
C/I channel 0, data change
C/I channel 1, data change
IOM-2 timing request
Table 4. Format of the Interrupt Register (IR), Read Only
Am79C30A/32A Data Sheet
DMR1 bit 0
DMR1 bit 1
DMR1 bit 3
DMR3 bit 0
DMR3 bit 1
PPIER bit 4
Interrupt Mask
DMR2 bit 0
DMR2 bit 1
DMR2 bit 2
DMR2 bit 3
DMR2 bit 4
DMR2 bit 5
DMR2 bit 6
DMR2 bit 7
DMR3 bit 6
MCR4 bit 3
LMR2 bit 3
LMR2 bit 6
LMR2 bit 4
LMR2 bit 5
DMR3 bit 2
DMR3 bit 3
DMR3 bit 4
DMR3 bit 5
EFCR bit 1
MF bit 1
MF bit 2
MF bit 3
PPIER bit 0
PPIER bit 1
PPIER bit 2
PPIER bit 3
PPIER bit 5
PPIER bit 6