AM79C32A Advanced Micro Devices, AM79C32A Datasheet - Page 41

• Manufacturer Part Number: AM79C32A
• Description: Digital Subscriber Controller (DSC) Circuit
• Manufacturer: Advanced Micro Devices

D-Channel Receive and Transmit Errors
Non-Integer Number of Bytes
A non-integer number of bytes occurs when the num-
ber of D-channel bits received between opening and
closing flags is not divisible by eight. If a received
packet consists of a non-integer number of bytes, the
DLC sets bit 1 in the D-channel Error Register (DER) to
a logical 1 when the last byte of the associated packet
is read from the D-channel Receive buffer.
Frame Check Sequence Error
If a received packet, including its 16-bit Frame Check
Sequence, is not received perfectly, the DLC sets DER
bit 3 to a logical 1 when the last byte of the associated
packet is read from the Receive buffer.
Receive Packet Abort
If seven contiguous 1s are received while receiving a
packet, the packet will be terminated. DER bit 0 will be
set to a logical 1 when the last byte of the associated
packet is read from the D-channel Receive buffer.
Overflow
Overflow occurs when the total number of D-channel
bytes within a packet (including, only when enabled,
the Frame Check Sequence bytes) exceeds the limit
contained in the D-channel Receive Byte Limit Regis-
ter. (See Receiving D-channel Packets section.) When
overflow occurs, the DLC terminates the packet, and
sets DER bit 4 to a logical 1 when the last byte of the
associated packet is read from the D-channel Receive
buffer.
DLC REGISTERS
The DLC contains the following registers.
Registers
First Received Byte Address Registers
Second Received Byte Address Registers
Transmit Address Register (16-bit)
D-channel Receive Byte Limit Register (16-bit)
D-channel Receive Byte Count Register (16-bit) (2-word FIFO)
D-channel Transmit Byte Count Register (16-bit)
Random Number Generator Registers
D-channel mode registers
Address Status Register (2-byte FIFO)
Extended FIFO Control Register
D-channel Transmit buffer Register
D-channel Receive buffer Register
D-channel Status Register #1
D-channel Status Register #2
D-channel Error Register (2-byte FIFO)
Am79C30A/32A Data Sheet
Underflow
If a received D-channel (including FCS) packet is less
than 5 bytes for a 2-byte address packet, an underflow
error condition occurs, and the DLC sets DER bit 5 to a
logical 1 when the last byte of the associated packet is
read from the D-channel Receive buffer.
Overrun
A D-channel overrun error occurs when the receiver
buffer is full, and another byte is received. This can
happen if the D-channel Receive buffer fills, and is not
read within 425 s. When this error occurs, the DLC
sets DER bit 6 to a logical 1 and terminates the packet.
Underrun
A D-channel underrun error occurs when an empty
D-channel buffer is transmitted. This can happen if the
D-channel Transmit buffer is not loaded within 375 s
of the D-channel Transmit buffer Empty interrupt being
asserted (IR bit 0). When this error occurs, the DLC
sets DER bit 7 to a logical 1 and terminates the packet.
Receive Packet Lost
Receive Packet Lost occurs when two outstanding
packets have been received and not serviced (the mi-
croprocessor has not read the DCRB register), and a
third packet is received. When this error occurs, DSR2
bit 2 is set to a logical 1 and the incoming packet is ter-
minated (not received).
Number of Registers Mnemonic
—
—
4
4
1
1
1
1
2
1
1
1
1
4
1
TAR
DRLR
DRCR
RNGR
FRAR
SRAR
DTCR
DMR
ASR
EFCR
DCTR
DCRB
DSR1
DSR2
DER
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