AK4640VG Asahi Kasei Microsystems, AK4640VG Datasheet - Page 24
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AK4640VG
Manufacturer Part Number
AK4640VG
Description
16BIT CODEC WITH MIC /HP/SPK-AMPl
Manufacturer
Asahi Kasei Microsystems
Datasheet
1.AK4640VG.pdf
(76 pages)
- Current page: 24 of 76
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ASAHI KASEI
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table 2 and Table 3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table 4
and the MCKO bit enables the MCKO output.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted. It takes X’tal
oscillator 20ms(typ) to be stable after PMXTL bit=“1”. The PLL needs 40ms lock time, whenever the sampling frequency
changes or the PLL is powered-up (PMPLL bit=“0” → “1”). If the sampling frequency is changed when the ADC or the
DAC operates (PMADC bit = “1” or PMDAC bit = “1”), the click noise may occur. The click noise of headphone and
speaker amps can be avoided by using the mute sequence examples (Figure 51 and Figure 52, respectively).
LRCK and BICK are output from the AK4640 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to
“L” (see Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present
whenever the AK4640 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the
AK4640 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”).
MS0273-E-00
System Clock
FS2
0
0
0
0
1
1
1
1
Mode
Mode
0
1
2
3
0
1
2
3
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
Table 2. MCKI Input Frequency (PLL Mode)
Table 3. Sampling Frequency (PLL Mode)
PLL1
FS1
PS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PLL0
FS0
PS0
- 24 -
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
11.2896MHz
12.288MHz
12MHz
MCKO
MCKI
11.025kHz
22.05kHz
256fs
128fs
N/A
44.1kHz
64fs
32fs
48kHz
32kHz
24kHz
16kHz
8kHz
Default
Default
Default
[AK4640]
2004/03
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