GAL20RA10B-10LJ Lattice Semiconductor, GAL20RA10B-10LJ Datasheet - Page 11

• Manufacturer Part Number: GAL20RA10B-10LJ
• Description: High-Speed Asynchronous E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

Circuitry within the GAL20RA10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1 s MAX). As a result,
the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous
Power-Up Reset
Input/Output Equivalent Schematics
(Vref Typical = 3.2V)
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Typical Input
Vcc
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
Vref
Q - OUTPUT
Vcc
CLK
Vcc
Vcc
Vcc (min.)
11
t
pr
nature of system power-up, some conditions must be met to
provide a valid power-up reset of the GAL20RA10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The regis-
ters will reset within a maximum of 1 s. As in normal system op-
eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.
Specifications GAL20RA10
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Data
Output
t
wl
t
su
Tri-State
Control
Feedback
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
(Vref Typical = 3.2V)
PIN
PIN