pal20ra10 Lattice Semiconductor Corp., pal20ra10 Datasheet
pal20ra10
Manufacturer Part Number
pal20ra10
Description
Gal20ra10 Gal High-speed Asynchronous E2 Cmos Pld Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.PAL20RA10.pdf
(15 pages)
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• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E
as 75mA typical I
when compared to bipolar counterparts. E
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20ra10_02
Features
— Independent Asynchronous Reset and Preset
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 9 ns Maximum from Clock Input to Data Output
— TTL Compatible 8 mA Outputs
— UltraMOS
— 75mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
— Independent Programmable Clocks
— Registered or Combinatorial with Polarity
— Full Function and Parametric Compatibility with
— 100% Functional Testability
— State Machine Control
— Standard Logic Consolidation
— Multiple Clock Logic Designs
2
CELL TECHNOLOGY
PAL20RA10
®
CC
Advanced CMOS Technology
which represents a substantial savings in power
2
CMOS circuitry achieves power levels as low
2
2
) floating gate technology to provide
CMOS
®
TECHNOLOGY
2
technology offers high
1
Functional Block Diagram
Pin Configuration
NC
High-Speed Asynchronous E
I
I
I
I
I
I
11
5
7
9
PL
12
4
I
I
I
I
I
I
I
I
I
I
GAL20RA10
Top View
PLCC
14
2
28
16
26
18
25
23
21
19
GAL20RA10
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
8
8
8
8
8
8
8
8
8
GND
8
PL
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
I
I
I
1
12
6
20RA10
GAL
2
DIP
CMOS PLD
July 1997
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OE
24
18
13
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OE
I/O/Q
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