GAL20RA10B-10LJ Lattice Semiconductor, GAL20RA10B-10LJ Datasheet
GAL20RA10B-10LJ
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GAL20RA10B-10LJ Summary of contents
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... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Industrial Grade Specifications Part Number Description GAL20RA10B Device Name Speed (ns Low Power Power Specifications GAL20RA10 ...
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Output Logic Macrocell (OLMC) The GAL20RA10 OLMC consists flip-flops with indi- vidual asynchronous programmable reset, preset and clock product terms. The sum of four product terms and an Exclusive-OR pro- vide a programmable polarity D-input to each ...
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Output Logic Macrocell Diagram PL OE Output Logic Macrocell Configuration (Registered With Polarity Output Logic Macrocell Configuration (Combinatorial With Polarity) OE Specifications GAL20RA10 XOR ( XOR ...
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GAL20RA10 Logic Diagram 1 ( 280 2 (3) 320 600 3 (4) 640 920 4 (5) 960 1240 5 (6) 1280 1560 6 (7) 1600 1880 7 (9) 1920 2200 8 (10) 2240 2520 9 (11) ...
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... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL20RA10B Recommended Operating Conditions (1) Commercial Devices: +1 ...
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... Preload Hold Time 1) Refer to Switching Test Conditions section. 2) Refer to fmax Descriptions section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL20RA10B Over Recommended Operating Conditions COM COM -7 -10 MIN. MAX. MIN. MAX ...
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Switching Waveforms INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O to Output Enable/Disable t wh CLK Clock Width ALL I/O PINS Parallel Preload OE t ...
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Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is cal- culated from measured tsu and tco. Switching Test Conditions Input Pulse Levels Input Rise and -7/-10 Fall Times ...
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... GAL20RA10 input buffers have active pull-ups within their input structure result, unused inputs and I/Os will float to a TTL “high” (logical “1”). Lattice Semiconductor recommends that all un- used inputs and tri-stated I/O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immu- nity and reduce Icc for the device ...
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Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL20RA10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1 ...
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GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 Temperature (deg. C) Delta Tpd ...
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GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.8 0.6 0.4 0 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc ...
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GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 ...
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GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage ...