M40SZ100 ST Microelectronics, M40SZ100 Datasheet - Page 12

• Manufacturer Part Number: M40SZ100
• Description: 5V or 3V NVRAM SUPERVISOR FOR LPSRAM
• Manufacturer: ST Microelectronics

M40SZ100Y, M40SZ100W
Battery Low Pin
The M40SZ100Y/W automatically performs bat-
tery voltage monitoring upon power-up, and at fac-
tory-programmed time intervals of at least 24
hours. The Battery Low (BL) pin will be asserted if
the battery voltage is found to be less than approx-
imately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced.
The M40SZ100Y/W only monitors the battery
when a nominal V
applications which require extensive durations in
the battery back-up mode should be powered-up
periodically (at least once every few months) in or-
der for this technique to be beneficial. Additionally,
if a battery low is indicated, data integrity should
be verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to V
chosen to control the rise time.
Power-fail Input/Output
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (independent from the
V
threshold (V
go low. This function is intended for use as an un-
der-voltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 7, page 5) to either the
unregulated DC input (if it is available) or the reg-
ulated output of the V
vider can be set up such that the voltage at PFI
falls below V
regulated V
microprocessor drops below the minimum operat-
ing voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
12/19
PFD
comparator). If PFI is less than the power-fail
CC
PFI
PFI
), the Power-Fail Output (PFO) will
input to the M40SZ100Y/W or the
several milliseconds before the
CC
is applied to the device. Thus
CC
regulator. The voltage di-
CC
should be
CC
is
curs after V
er returns, PFO is forced high, irrespective of V
for the write protect time (t
from V
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to V
left unconnected.
V
I
switching, can produce voltage fluctuations, re-
sulting in spikes on the V
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
below V
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
mends connecting a schottky diode from V
V
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
Figure 13. Supply Voltage Protection
CC
CC
SS
transients, including those produced by output
Noise And Negative Going Transients
(cathode connected to V
PFD
SS
V CC
(max) until the inputs are recognized. At
by as much as one volt. These negative
CC
0.1 F
drops below V
CC
CC
REC
bus. These transients
PFD
CC
that drive it to values
CC
), which is the time
V CC
V SS
(min). When pow-
bus. The energy
, anode to V
DEVICE
SS
AI00622
and PFO
CC
SS
PFI
to
).