M40SZ100 ST Microelectronics, M40SZ100 Datasheet - Page 10

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M40SZ100

Manufacturer Part Number
M40SZ100
Description
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
Manufacturer
ST Microelectronics
Datasheet

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M40SZ100Y, M40SZ100W
Figure 11. Power Up Timing
Table 6. Power Down/Up AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
10/19
Symbol
t
t
t
t
t
t
t
FB
t
CER
REC
WPT
2. V
3. V
PFD
EPD
F
t
RB
R
(2)
(3)
passes V
PFD
PFD
V CC
V PFD (max)
V PFD
V PFD (min)
V SO
E
E CON
RST
PFO
(min) to V
(max) to V
V
V
PFI to PFO Propagation Delay
V
Chip Enable Propagation Delay (Low or High)
V
Chip Enable Recovery
V
Write Protect Time
PFD
PFD
PFD
PFD
SS
PFD
(min).
to V
(min) to V
(max) to V
(min) to V
(max) to RST High
SS
PFD
PFD
fall time of less than tFB may cause corruption of RAM data.
(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after V
tRB
(min) V
V OHB
PFD
SS
PFD
V
(max) V
CC
CC
(min) V
Fall Time
Rise Time
Parameter
CC
CC
Rise Time
A
Fall Time
tR
= –40 to 85°C; V
tCER
(1)
tREC
CC
= 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
M40SZ100W
M40SZ100Y
tEPD
Min
300
VALID
10
15
10
40
40
40
1
Max
120
200
200
25
10
15
AI03937
tEPD
Unit
ms
ms
µs
µs
µs
µs
µs
µs
ns
ns
CC

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