X5083 Xicor, X5083 Datasheet - Page 5

• Manufacturer Part Number: X5083
• Description: CPU Supervisor with 8Kbit SPI EEPROM
• Manufacturer: Xicor

X5083
Figure 4. V
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus
REV 1.1.6 6/25/02
TRIP
Programming Sequence
Emax = Maximum Desired Error
Old V
New V
CC
CC
Applied + Error
Applied =
Error
–Emax
NO
www.xicor.com
Set V
™
(V
V
TRIP
Apply 5V to V
Decrement V
CC
Measured V
CC
Desired V
goes active?
Desired V
Reset V
RESET pin
Sequence
Sequence
Set V
= V
Execute
Execute
activity within the user selectable time out period or the
supply voltage falls below a preset minimum V
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
= V
Programming
DONE
CC
CC
TRIP
YES
–Emax < Error < Emax
TRIP
- 50mV)
TRIP
Applied =
TRIP
TRIP
CC
CC
-
Error
Characteristics subject to change without notice.
Emax
Old V
New V
CC
Reset V
Sequence
CC
Execute
Applied - Error
Applied =
TRIP
TRIP
5 of 21
.