X5083 Xicor, X5083 Datasheet - Page 14
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X5083
Manufacturer Part Number
X5083
Description
CPU Supervisor with 8Kbit SPI EEPROM
Manufacturer
Xicor
Datasheet
1.X5083.pdf
(21 pages)
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X5083
Data Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
Serial Output Timing
Serial Input Timing
REV 1.1.6 6/25/02
Symbol
t
t
f
RO
t
FO
SCK
t
DIS
HO
t
V
(4) t
SCK
(3)
SCK
(3)
SO
CS
SO
CS
SI
SI
write cycle.
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
LSB IN
ADDR
t
SU
High Impedance
MSB IN
MSB Out
t
LEAD
t
V
t
H
t
CYC
Parameter
MSB–1 Out
www.xicor.com
t
HO
t
t
RI
WH
t
WL
Characteristics subject to change without notice.
t
Min.
FI
0
0
LSB IN
LSB Out
2.7V–5.5V
t
CS
Max.
150
130
3.3
50
50
t
LAG
t
t
DIS
LAG
Unit
MHz
ns
ns
ns
ns
ns
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