X4003 Xicor, X4003 Datasheet - Page 3

• Manufacturer Part Number: X4003
• Description: CPU Supervisor
• Manufacturer: Xicor

X4003/X4005
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4003/X4005 activates a
power on reset circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to
– It allows time for an FPGA to download its configura-
When V
for 200ms (nominal) the circuit releases RESET/
RESET, allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the V
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
Set V
V
The X4003/X4005 is shipped with a standard V
threshold (V
over normal operating and storage conditions. How-
ever, in applications where the standard V
exactly right, or if higher precision is needed in the
V
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
REV 1.1.3 4/30/02
CC
TRIP
to operate with insufficient voltage.
stabilization of the oscillator.
tion prior to initialization of the circuit.
SDA
SCL
WP
THRESHOLD RESET PROCEDURE
TRIP
value, the X4003/X4005 threshold may be
CC
Level Sequence (V
exceeds the device V
TRIP
) voltage. This value will not change
0 1 2
A0h
3
4 5 6 7
TRIP
CC
. The RESET/RESET
TRIP
= desired V
threshold value
0 1 2 3 4 5 6 7
TRIP
TRIP
www.xicor.com
is not
V
value)
P
CC
CC
= 15-18V
01h
signal remains active until the voltage drops below 1V.
It also remains active until V
V
Watchdog Timer
The watchdog timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvol-
atile control bits in the control register determine the
watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
Setting the V
This procedure is used to set the V
voltage value. For example, if the current V
and the new V
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
SCL
SDA
TRIP
Start
Condition
for 200ms.
0 1 2 3 4 5 6 7
TRIP
TRIP
.6µs
Characteristics subject to change without notice.
00h
Voltage
is 4.6V, this procedure will directly
CC
Restart
returns and exceeds
.6µs
TRIP
TRIP
Stop
Condition
to a higher
is 4.4V
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