COP8SE National Semiconductor, COP8SE Datasheet - Page 15

• Manufacturer Part Number: COP8SE
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
• Manufacturer: National Semiconductor

Reserved
5.0 Functional Description
5.10 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
PSW Register (Address X'00EF)
The PSW register contains the following bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
Bit 7
Bit 7
Bit 7
T1C3
HC
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA
EXPND
BUSY
EXEN
GIE
Reserved This bit is reserved and must be set to zero
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
T1ENB
C
T1C2
LPEN
T1PNDA
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T0PND
T1C1
T1ENA
T0EN
T1C0
EXPND
µWPND
MSEL
µWEN
BUSY
IEDG
T1PNDB
(Continued)
EXEN
SL1
T1ENB
Bit 0
GIE
Bit 0
SL0
Bit 0
15
6.0 Timers
Each device contains a very versatile set of timers (T0 and
T1). All timers and associated autoreload/capture registers
power up containing random data.
6.1 TIMER T0 (IDLE TIMER)
Each device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
Figure 11 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the Idle Timer register can be selected
for triggering the IDLE Timer interrupt. Each time the se-
lected bit underflows (every 4k, 8k, 16k, 32k or 64k instruc-
tion cycles), the IDLE Timer interrupt pending bit T0PND is
set, thus generating an interrupt (if enabled), and bit 6 of the
Port G data register is reset, thus causing an exit from the
IDLE mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer in-
terrupt enable bit T0EN must be set, and the GIE (Global In-
terrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bits 3–7 of the ITMR Register are reserved and
must be “0”.
The ITMR register is cleared on Reset and the Idle Timer pe-
riod is reset to 4,096 instruction cycles.
ITMR Register (Address X’0xCF)
Any time the IDLE Timer period is changed there is the pos-
sibility of generating a spurious IDLE Timer interrupt by set-
ting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before at-
tempting to synchronize operation to the IDLE Timer.
ITSEL2
Bit 7
0
0
0
0
1
Reserved (Must be 0 )
TABLE 3. Idle Timer Window Length
ITSEL1
0
0
1
1
X
ITSEL0
0
1
0
1
X
Bit 3
C
. The user cannot read or
ITSEL2
(Instruction Cycles)
Idle Timer Period
16,384
32,768
65,536
ITSEL1
4,096
8,192
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ITSEL0
Bit 0