COP8SE National Semiconductor, COP8SE Datasheet - Page 13

• Manufacturer Part Number: COP8SE
• Description: 8-Bit CMOS ROM Based and OTP Microcontrollers with 4k Memory and 128 Bytes EERAM
• Manufacturer: National Semiconductor

5.0 Functional Description
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always lo-
cated in the base segment. The stack pointer will be initial-
ized to point at data memory location 006F as a result of re-
set.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The 128 bytes of EERAM in this de-
vice are memory mapped at address locations 0100 to 017F.
5.6 SECURITY FEATURE (COP8SER7 only)
The program memory array has an associated Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature and can only be asserted after
the memory array has been programmed and verified. A se-
cured part will read 00(hex) by a programmer. The part will
fail Blank Check and will fail Verify operations. A READ op-
eration will fill the programmer’s memory with 00(hex). The
Security Byte itself is always readable with value of 00(hex)
if unsecure and FF(hex) if secure.
5.7 RESET
The devices are initialized when the RESET pin is pulled low.
The following occurs upon initialization:
Port L: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
Accumulator, Timer 1:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
(Continued)
13
DOG logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
5.8.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up initial-
ization, the user must ensure that the RESET pin is held low
until the device is within the specified V
circuit on the RESET pin with a delay 5 times (5x) greater
than the power supply rise time is recommended. Reset
should also be wide enough to ensure crystal start-up upon
Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in Fig-
ure 9 .
RC
5.9 OSCILLATOR CIRCUITS
These devices can be driven by a clock input on the CKI in-
put pin which can be between DC and 10 MHz. The CKO
output clock is on pin G7 (crystal configuration). The CKI in-
put frequency is divided down by 10 to produce the instruc-
tion cycle clock (1/t
Figure 10 shows the crystal and R/C oscillator connection
diagram.
S Register: CLEARED
E2CFG: Cleared except the E2BUSY Bit (Bit 1)
EERAM: Unaffected
ITMR: Cleared
RAM:
WATCHDOG (if enabled):
>
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
The device comes out of reset with both the WATCH-
5x power supply rise time.
FIGURE 9. Reset Circuit Using External Reset
C
).
C
clock cycles. The Clock Monitor bit
C
–32 t
C
clock cycles following
DS100973-14
CC
voltage. An R/C
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