COP8ACC5 National Semiconductor, COP8ACC5 Datasheet - Page 34

• Manufacturer Part Number: COP8ACC5
• Description: 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
• Manufacturer: National Semiconductor

www.national.com
SBIT
RBIT
IFBIT
RPND
X
X
LD
LD
LD
LD
LD
X
X
LD
LD
LD
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
Instruction Set
# ,Mem
# ,Mem
# ,Mem
A,Mem
A,[X]
A,Meml
A,[X]
B,Imm
Mem,Imm
Reg,Imm
A, [B
A, [X
A, [B
A, [X
[B
A
A
A
A
A
A
A
A
A
Addr.
Addr.
Disp.
Addr.
Addr
±
],Imm
±
±
±
±
]
]
]
]
(Continued)
Reset PeNDing Flag
CLeaR A
INCrement A
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Set C
Set BIT
Reset BIT
IF BIT
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
Rotate A Left thru C
SWAP nibbles of A
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
34
Reset Software Interrupt Pending Flag
A
A
A
A
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
If bit # ,A or Mem is true do next instruction
A
A
A
A
B
Mem
Reg
A
A
A
A
[B]
A
C
C
A7...A4
C
C
IF C is true, do next instruction
If C is not true, do next instruction
SP
[SP]
PU
PC
PC9...0
PC
[SP] PL, [SP-1]
[SP] PL, [SP-1]
PL ROM (PU,A)
SP + 2, PL
SP + 2, PL
SP + 2, PL
[SP]
PC
Meml
[X]
Imm
[B], (B
[X], (X
0
A + 1
A − 1
ROM (PU,A)
BCD correction of A (follows ADC, SUBC)
A7
A7
1, HC
0, HC
Mem
[X]
[B], (B
[X], (X
PC + 1
Imm, (B
SP + 1, A
[VU], PL [VL]
ii (ii = 15 bits, 0 to 32k)
PC + r (r is −31 to +32, except 1)
PL, [SP-1]
Imm
A, SP
Imm
...
i (i = 12 bits)
A3...A0
...
[SP], PU
[SP],PU
X
[SP],PU
1
0
B
X
B
±
A0
±
±
A0
SP − 1
±
1)
B
1)
1)
1)
±
[SP]
PU,SP-2, PC
PU,SP-2, PC9...0
PU, SP-2, PC
1)
C
C
[SP-1], skip next instruction
[SP-1]
[SP-1],GIE 1
ii
0FF
i