ST62P08C ST Microelectronics, ST62P08C Datasheet - Page 27

• Manufacturer Part Number: ST62P08C
• Description: (ST62P08C - ST62P20C) 8-BIT MCU
• Manufacturer: ST Microelectronics

6 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in Figure 18.
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see Table 8). In
the vector location, the user must write a Jump in-
Figure 17. Interrupts Block Diagram
PB0...PB7
PA0...P A3
* Depending on device. See device summary on page 1.
NMI
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
CONFIGURATION
CONFIGURATION
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
A/D CONVERTER *
V DD
TIMER
(ADCR REGISTER)
(TSCR REGISTER)
LATCH
(IOR REGISTER)
EOC BIT
TMZ BIT
EAI BIT
ETI BIT
AT START OF VECTOR #0 ROUTINE
CLEARED BY H/W
CLEARED BY H/W
AT START OF
VECTOR #1 ROUTINE
ESB BIT
LATCH
CLEARED
BY H/W AT START OF
VECTOR #2 ROUTINE
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
LATCH
(IOR REGISTER)
ST6208C/ST6209C/ST6210C/ST6220C
LES BIT
(IOR REGISTE R)
0
1
GEN BIT
VECTOR #0
VECTOR #1
VECTOR #3
VECTOR #4
VECTO R #2
EXIT FROM
STOP/WAI T
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