ST62P08C ST Microelectronics, ST62P08C Datasheet - Page 24
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ST62P08C
Manufacturer Part Number
ST62P08C
Description
(ST62P08C - ST62P20C) 8-BIT MCU
Manufacturer
ST Microelectronics
Datasheet
1.ST62P08C.pdf
(105 pages)
Available stocks
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ST6208C/ST6209C/ST6210C/ST6220C
5.3 RESET
5.3.1 Introduction
The MCU can be reset in three ways:
5.3.2 RESET sequence
The basic RESET sequence consists of 3 main
phases:
The 2048 clock cycle delay allows the oscillator to
stabilise and ensures that recovery has taken
place from the Reset state.
Figure 13. RESET Sequence
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1
A low pulse input on the RESET pin
Internal Watchdog reset
Internal Low Voltage Detector (LVD) reset
Internal (watchdog or LVD) or external Reset
event
A delay of 2048 clock (f
RESET vector fetch
WATCHDOG
RESET PIN
INTERNAL
RESET
RESET
RESET
LVD
V
V
IT+
IT-
V
RUN
DD
INT
RESET
) cycles
RUN
RESET
WATCHDOG UNDERFLOW
The RESET vector fetch phase duration is 2 clock
cycles.
When a reset occurs:
– The stack is cleared
– The PC is loaded with the address of the Reset
A jump to the beginning of the user program must
be coded at this address.
– The interrupt flag is automatically set, so that the
vector. It is located in program ROM starting at
address 0FFEh.
CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
RUN
RESET
2048 CLOCK CYCLE (f INT ) DELAY
RUN