IS42S16100 Integrated Silicon Solution, IS42S16100 Datasheet - Page 29

• Manufacturer Part Number: IS42S16100
• Description: 512K Words x 16Bits x 2 Banks Synchronous Dynamic RAM
• Manufacturer: Integrated Silicon Solution

IS42S16100
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
11/01/01
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new write
command is executed. To prevent collision between input
and output data at the I/On pins during this operation, the
CAS latency = 2, 3, burst length = 4
COMMAND
U/LDQM
CLK
I/O
READ (CA=A, BANK 0)
READ A0
HI-Z
D
WRITE B0
IN
t
CCD
B0
WRITE (CA=B, BANK 0)
D
IN
B1
D
IN
B2
output data must be masked using the U/LDQM pins. The
interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
IN
CCD
B3
) between these commands must be at least
ISSI
29
®