SAF-C161S Infineon Technologies, SAF-C161S Datasheet - Page 68
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SAF-C161S
Manufacturer Part Number
SAF-C161S
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C161S.pdf
(75 pages)
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Table 19
ALE cycle time = 4 TCL + 2
Parameter
Data hold after WR
ALE rising edge after RD,
WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to
RdCS, WrCS (with
RW-delay)
ALE falling edge to
RdCS, WrCS (no
RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data Sheet
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
1)
3)
2)
3)
3)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
24
26
28
38
39
41
42
43
46
47
48
49
50
51
53
t
A
+
t
C
CC 15 +
CC -12 +
CC 0 +
CC -8 -
SR –
CC 9 +
CC 19 +
CC -6 +
SR –
SR –
CC 38 +
CC 63 +
CC 28 +
SR 0
SR –
+
t
F
Min.
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
t
t
= 20 MHz
t
F
F
64
t
A
t
t
t
t
t
A
F
t
A
C
C
C
F
Max.
–
–
–
10 -
47 +
t
–
–
–
20 +
45 +
–
–
–
–
30 +
C
+ 2
t
t
t
t
A
t
C
C
F
A
1 / 2TCL = 1 to 20 MHz
Min.
TCL - 10
+
-12 +
0 +
-8 -
–
TCL - 16
+
TCL - 6
+
-6
+
–
–
2TCL - 12
+
3TCL - 12
+
2TCL - 22
+
0
–
Variable CPU Clock
t
t
t
t
t
t
t
F
F
A
A
C
C
C
t
t
F
A
Timing Characteristics
t
F
Max.
–
–
–
10 -
3TCL - 28
+
–
–
–
2TCL - 30
+
3TCL - 30
+
–
–
–
–
2TCL - 20
+ 2
t
t
t
C
C
C
t
A
+ 2
t
V1.0, 2003-11
A
+
t
t
F
A
1)
C161S
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns