SAF-C161S Infineon Technologies, SAF-C161S Datasheet - Page 15
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SAF-C161S
Manufacturer Part Number
SAF-C161S
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C161S.pdf
(75 pages)
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C161S
Functional Description
3.1
Memory Organization
The memory space of the C161S is configured in a von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 Mbytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C161S is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment 0 or segment 1.
2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2
512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the
microcontroller. The maximum contiguous external address space is 4 Mbytes, i.e. this
is the maximum address window size. Using the chip-select lines (multiple windows) this
results in a maximum usable external address space of 16 Mbytes.
Data Sheet
11
V1.0, 2003-11