HCPL-316 ETC, HCPL-316 Datasheet - Page 10

• Manufacturer Part Number: HCPL-316
• Description: 2.0 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback
• Manufacturer: ETC

Notes:
1. In accordance with UL1577, each
2. The Input-Output Momentary With-
3. Device considered a two terminal
5. Maximum pulse width = 10 s,
4. In order to achieve the absolute
optocoupler is proof tested by
applying an insulation test voltage
detection current limit, I
This test is performed before the
100% production test for partial
discharge (method b) shown in VDE
0884 Insulation Characteristic Table,
if applicable.
stand Voltage is a dielectric voltage
rating that should not be interpreted
as an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or VDEO884
Insulation Characteristics Table.
device: pins 1 - 8 shorted together
and pins 9 - 16 shorted together.
maximum power dissipation
specified, pins 4, 9, and 10 require
ground plane connections and may
require airflow. See the Thermal
Model section in the application notes
at the end of this data sheet for
details on how to estimate junction
temperature and power dissipation. In
most cases the absolute maximum
output IC junction temperature is the
limiting factor. The actual power
dissipation achievable will depend on
the application environment (PCB
Layout, air flow, part placement,
etc.). See the Recommended PCB
Layout section in the application
notes for layout considerations.
Output IC power dissipation is
derated linearly at 10 mW/ C above
90 C. Input IC power dissipation does
not require derating.
maximum duty cycle = 0.2%. This
value is intended to allow for compo-
nent tolerances for designs with I
peak minimum = 2.0 A. See
Applications section for additional
details on I
from 3.0 A at +25 C to 2.5 A at
+100 C. This compensates for
increased I
V
OL
4200 Vrms for 1 second (leakage
over temperature.
OPEAK
OH
peak. Derate linearly
due to changes in
I-O
5 A).
O
10. Maximum pulse width = 1.0 ms,
11. Once V
12. See the Blanking Time Control
13. This is the “increasing” (i.e. turn-on
14. This is the “decreasing” (i.e. turn-off
15. This load condition approximates the
16. Pulse Width Distortion (PWD) is
17. As measured from V
18. The difference between t
19. Supply Voltage Dependent.
20. This is the amount of time from when
6. This supply is optional. Required only
7. Maximum pulse width = 50 s,
8. See the Slow IGBT Gate Discharge
9. 15 V is the recommended minimum
when negative gate drive is
implemented.
maximum duty cycle = 0.5%.
During Fault Condition section in the
applications notes at the end of this
data sheet for further details.
operating positive supply voltage
(V
margin in excess of the maximum
V
Level Output Voltage testing, V
measured with a dc load current.
When driving capacitive loads, V
will approach V
zero units.
maximum duty cycle = 20%.
allowed to go high (V
V
of the HCPL-316J will be the primary
source of IGBT protection. UVLO is
needed to ensure DESAT is
functional. Once V
DESAT will remain functional until
V
detection and UVLO features of the
HCPL-316J work in conjunction to
ensure constant IGBT protection.
section in the applications notes at
the end of this data sheet for further
details.
or “positive going” direction) of
V
or “negative going” direction) of
V
gate load of a 1200 V/75A IGBT.
defined as |t
unit.
between any two HCPL-316J parts
under the same test conditions.
the DESAT threshold is exceeded,
until the FAULT output goes low.
CC2
CC2
UVLO+
UVLO
UVLO-
CC2
- V
- V
), the DESAT detection feature
- V
OUT
< 12.4 V. Thus, the DESAT
E
E
threshold of 13.5 V. For High
.
.
E
) to ensure adequate
of the HCPL-316J is
PHL
CC
- t
UVLO+
as I
PLH
IN+
CC2
OH
| for any given
, V
PHL
approaches
- V
> 11.6 V,
IN-
E
to V
and t
>
OH
OH
OUT
PLH
is
.
10
21. This is the amount of time the DESAT
22. This is the amount of time from when
23. Common mode transient immunity in
24. Common mode transient immunity in
25. Does not include LED2 current
26. To clamp the output voltage at
27. The recommended output pull-down
28. In most applications V
threshold must be exceeded before
V
FAULT output to go low.
RESET is asserted low, until FAULT
output goes high. The minimum
specification of 3 s is the guaranteed
minimum FAULT signal pulse width
when the HCPL-316J is configured
for Auto-Reset. See the Auto-Reset
section in the applications notes at
the end of this data sheet for further
details.
the high state is the maximum
tolerable dV
mode pulse, V
output will remain in the high state
(i.e., V
100 pF and a 3K
needed in fault detection mode.
the low state is the maximum
tolerable dV
mode pulse, V
output will remain in a low state (i.e.,
V
during fault or blanking capacitor
discharge current.
V
between the output and V
recommended to sink a static current
of 650 A while the output is high.
See the Output Pull-Down Resistor
section in the application notes at the
end of this data sheet if an output
pull-down resistor is not used.
resistor between V
not contribute any output current
when V
powered up first (before V
powered down last (after V
is desirable for maintaining control of
the IGBT gate. In applications where
V
important to ensure that V
low until V
operating voltage (minimum 4.5 V) to
avoid any momentary instability at
the output during V
ramp-down.
OUT
O
CC
CC2
< 1.0 V or FAULT < 0.8 V).
- 3 V
begins to go low, and the
is powered up first, it is
O
OUT
> 15 V or FAULT > 2 V). A
BE
CC1
, a pull-down resistor
= V
CM
CM
CM
CM
/dt of the common
/dt of the common
reaches the proper
EE
, to assure that the
, to assure that the
.
OUT
CC1
pull-up resistor is
CC1
and V
ramp-up or
EE
will be
CC2
in+
CC2
is
EE
) and
remains
). This
does