M66256 Mitsubishi, M66256 Datasheet - Page 8

• Manufacturer Part Number: M66256
• Description: 5120 x 8-BIT LINE MEMORY (FIFO)
• Manufacturer: Mitsubishi

8
VARIABLE LENGTH DELAY BITS
• 1-line (5120 bits) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
• N-bit delay bit
(Making a reset at a cycle corresponding to delay length)
WCK
RCK
WRES
RRES
D
Q
WCK
RCK
WRES
RRES
D
Q
n
n
n
n
t
t
RESS
RESS
t
t
RESH
RESH
Cycle 0
Cycle 0
t
t
DS
DS
(0)
(0)
t
t
DH
DH
Cycle 1
Cycle 1
(1)
(1)
Cycle 2
Cycle 2
5120 cycles
m cycles
(2)
(2)
(n–3)
(5117)
Cycle 5118 Cycle 5119
Cycle n–2
(n–2)
(5118)
Cycle n–1
t
RESS
(n–1)
(5119)
Cycle 5120
t
RESH
Cycle n
t
t
AC
AC
(0')
(0')
t
t
DS
DS
(0')
(0)
(0')
(0)
t
t
DH
t
t
OH
Cycle 5121
Cycle n+1
OH
5120
DH
(1')
(1')
MITSUBISHI DIGITAL ASSP
(1')
(1)
(1')
(1)
8-BIT LINE MEMORY (FIFO)
Cycle 5122
Cycle n+2
(2')
(2')
(2')
(2)
(2')
(2)
M66256FP
Cycle n+3
WE, RE = “L”
m
WE, RE = “L”
(3')
3
(3')
(3)
(3')
(3)