M66256 Mitsubishi, M66256 Datasheet
M66256
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M66256 Summary of contents
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... DESCRIPTION The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between de- vices with different data processing throughput ...
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... GND GND, Output open 25ns WCK RCK f = 1MHz f = 1MHz MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO synchronization with rise 0 7 Ratings Unit –0.5 ~ +7.0 V –0 0 –0 0 440 mW –65 ~ 150 C Unit Max ...
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... 10%, GND = 0V Parameter = 5V 10%, GND = 0V, unless otherwise noted) CC Parameter – WRES “L” level period – RRES “L” level period MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) Limits Unit Min. Typ. Max ...
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... OEN RCK =30pF : 10% of output amplitude and t is 90% of ODIS(HZ) 1.3V t ODIS(HZ) 90% t ODIS(LZ) 10% MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO =1k L SW1 Q n SW2 C =5pF : OEN ODIS R =1k L Parameter SW1 t Closed ...
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... Disable cycle WCKL NWEH WEH NWES n+1) (n+2) Reset cycle Cycle RESS RESH (n) MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) Cycle n+3 Cycle n+4 t WES (n+3) (n+4) WRES = “H” Cycle 1 Cycle 2 t NRESS (0) (1) ( “L” 5 ...
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... To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well. 6 MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) n cycle ...
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... RCKL REH NRES NREH t ODIS HIGH-Z (n+1) (n+2) Reset cycle Cycle RESS RESH t AC (n) (0) (0) MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) Cycle n+3 Cycle n+4 t RES OEN (n+3) (n+ RRES = “H” Cycle 1 Cycle 2 NRESS (0) (1) ( “L” ...
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... Cycle 5118 Cycle 5119 (1) (2) (5117) (5118) (5119) 5120 cycles Cycle 2 Cycle n–2 Cycle n–1 t RESS (1) (2) (n–3) (n–2) (n–1) m cycles MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) Cycle 5120 Cycle 5121 Cycle 5122 (0') (1') (2 (0') (1') (2') (3 ...
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... Cycle 2 Cycle n–1 Cycle n Cycle n+1 Cycle n+2 Cycle n NREH RES (2) (n–2) (n–1) ( cycles AC OH (0) MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO (n+1) (n+2) (n+3) (1) (2) (3) WE "L" (n+1) (n+2) (n+3) (1) (2) ( “L” ...
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... WCK (n–1)<1> Cycle n <0>* RCK (n–1)<0> Cycle n+1 Cycle n+2 (n) (n+1) Cycle n–2 Cycle n–1 Cycle 0 <2>* (n)<1>* (00) <2>* Cycle 0 <1>* (0)<1>* (n)<0>* MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) of cycle n becomes invalid. n Cycle n+3 (n+2) (n+3) Cycle n invalid (n) Cycle n <2>* (n–1)<2>* (n)<2>* Cycle n <1>* (n–1)<1>* (n)<1>* <0>*, <1>* and <2>* indicates a line value. ...
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... N B Line n image data 1-line delay Line (n–1) image data 1-line delay Line (n–1) Line N+K { (N–A)+(N–B)} = N+K { 2N–(A+B)} Line (n+ Laplacean coefficient MITSUBISHI DIGITAL ASSP M66256FP 5120 8-BIT LINE MEMORY (FIFO) N Corrected image data K 11 ...