F25L32PA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32PA-100PAG Datasheet - Page 16

• Manufacturer Part Number: F25L32PA-100PAG
• Description: 3V Only 32 Mbit Serial Flash Memory with Dual
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Fast Read Dual I/O (50 MHz~100 MHz)
The Fast Read Dual I/O (BBH) instruction is similar to the Fast
Read Dual Output (3BH) instruction, but with the capability to
input address bits [A
To set mode bits [M
further reduce instruction overhead (See Figure 5). The upper
mode bits [M
instruction with/without the first byte command code (BBH). The
lower mode bits [M
Elite Semiconductor Memory Technology Inc.
Figure 5: Fast Read Dual I/O Sequence ([M
Figure 6: Fast Read Dual I/O Sequence ([M
7
SIO
SCK
–M
SIO
CE
Note: The mode bits [M3 -M0] are “d on’t care”.
0
1
4
] controls the length of next Fast Read Dual I/O
MODE3
MODE0
3
However , the IO pins sh ould be high-impefance piror to the falling edge of the first data clock.
–M
SCK
23
SIO
SIO
CE
7
Note: The mode bits [M3 -M0] are “don’t care”.
-A
-M
0
0
1
] are “don’t care”.
0
HIG H IMPENANCE
MODE0
] two bits per clock.
MODE3
0
However , the IO pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock.
] after the address bits [A
MSB
0 1 2 3 4 5 6 7 8
22 20 18 16
23 21
BB
A
23- 16
19 17
14 12 10 8
15 13 11 9
7
7
22 20 18 16
23 21
-M
-M
A
15- 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A
0
0
23-16
19 17
] = 0xH or NOT AxH)
] = AxH)
6
7
23
14 12 10 8
15 13 11 9
4 2
5
A
-A
7-0
A
3 1
0
15-8
] can
0
6
7
6
7
4
5
M
4 2
5
A
7-0
7- 0
3
If [M
(See Figure 6). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M
CE is raised and the lowered) doesn’t need the command code
0
1
6 4 2 0
7 5 3 1
6
7
D
7
OUT
N
4
5
–M
M
7- 0
IO
0
] = “AxH”, the next Fast Read Dual I/O instruction (after
0
6 4 2 0
7 5 3 1
switches from In put to Ouput
6 4 2 0
7 5 3 1
D
N+1
OUT
D
OUT
N
7
7
IO
27 28
6 4 2 0
7 5 3 1
–M
–M
0
6 4 2 0
7 5 3 1
D
switches from Input to Ouput
N+2
OU T
0
0
D
N+1
] are the value other than “AxH”, the next
] before issuing normal instructions.
OU T
31 32
6 4 2 0
7 5 3 1 7 5
Publication Date: Mar. 2009
Revision: 1.0
6 4 2 0
7 5 3 1
D
N+3
D
OUT
N+2
OUT
35 36
6 4
F25L32PA
6 4 2 0
7 5 3 1 7 5
D
N+4
OUT
D
N+3
OUT
39 40
6 4
D
N+4
OUT
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