F25L32PA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32PA-100PAG Datasheet - Page 15

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F25L32PA-100PAG

Manufacturer Part Number
F25L32PA-100PAG
Description
3V Only 32 Mbit Serial Flash Memory with Dual
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet

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Part Number
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Quantity
Price
Part Number:
F25L32PA-100PAG
Manufacturer:
NXP
Quantity:
32
ESMT
Fast Read Dual Output (50 MHz~100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on bidirectional I/O pins (SIO
transferred from the device at twice the rate of standard SPI
devices. This instruction is for quickly downloading code from
Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
Elite Semiconductor Memory Technology Inc.
Figure 4: Fast Read Dual Output Sequence
SIO
SCK
SIO
CE
Note: The input data durin g the dummy clocks is “don’t care”.
0
1
MODE3
MODE0
However , the IO
MSB
0 1 2 3 4 5 6 7 8
0
and SIO
0
pin should be high-impefance piror to th e falling edge of the first data clock.
3B
HIGH IMPENANCE
1
). This allows data to be
MSB
ADD.
15 16
ADD.
23 24
ADD.
31 32
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Dummy
39 40
6 4 2 0
7 5 3 1
D
OUT
N
43 44
IO
0
6 4 2 0
7 5 3 1
switches from In put to Ouput
D
N+1
OUT
47 48
6 4 2 0
7 5 3 1
Publication Date: Mar. 2009
Revision: 1.0
D
N+2
OU T
51 52
6 4 2 0
7 5 3 1 7 5
F25L32PA
D
N+3
OU T
55 56
6 4
D
N+4
OUT
23
-A
0
] and a
15/36

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