HT82B40A HOLTEK [Holtek Semiconductor Inc], HT82B40A Datasheet - Page 33

• Manufacturer Part Number: HT82B40A
• Description: I/O MCU with USB Interface
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. The MISC will be cleared by the USB reset signal.
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which the address is
listed in the following table. After reading the current data, the next data will show after 2 s, this is used to check the
endpoint FIFO status and response to the MISC register, if the read/write action is still going on.
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform read-
ing, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writ-
ing and clearing.
Note:
Rev. 1.10
Read FIFO0 sequence
Write FIFO1 sequence
Check whether FIFO0 can be read or not
Check whether FIFO1 can be written or not
Read 0-sized packet sequence form FIFO0
Write 0-sized packet sequence to FIFO1
Bit No.
0
1
2
4
3
5
6
7
Registers
*: There is a 2 s time between 2 read actions or between 2 write actions.
FIFO0
FIFO1
FIFO2
READY
CLEAR
SELP1
SELP0
SCMD
Label
LEN0
REQ
TX
Actions
R/W
R/W
R/W
R/W Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
R/W
R/W
R/W
R
After setting the other status of the desired one in the MISC, endpoint FIFO can be
requested by setting this bit to 1 . After the task is completed, this bit must be
cleared to 0 .
This bit defines the direction of data transferring between the MCU and endpoint
FIFO. When the TX is set to 1 , this means that the MCU wants to write data to the
endpoint FIFO. After the task is completed, this bit must be cleared to 0 before ter-
minating the request to represent the end of transferring. For a read action, this bit
has to be cleared to 0 to represent that MCU wants to read data from the endpoint
FIFO and has to be set to 1 after completion.
Defines which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: reserved
Used to show that the data in the endpoint FIFO is a SETUP command. This bit has
to be cleared by firmware. That is to say, even if the MCU is busy, the device will not
miss any SETUP commands from the host.
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready for operation.
Used to indicate that a 0-sized packet has been sent from a host to the MCU. This bit
should be cleared by firmware.
R/W
R/W
R/W
R/W
MISC (46H) Register
00H 01H delay 2 s, check 41H read* from FIFO0 register and
check not ready (01H) 03H 02H
0AH 0BH delay 2 s, check 4BH write* to FIFO1 register and
check not ready (0BH) 09H 08H
00H 01H delay 2 s, check 41H (ready) or 01H (not ready) 00H
0AH 0BH delay 2 s, check 4BH (ready) or 0BH (not ready) 0AH
00H 01H delay 2 s, check 81H read once (01H) 03H 02H
0AH 0BH delay 2 s, check 0BH 0FH 0DH 08H
Bank
33
1
1
1
MISC Setting Flow and Status
Function
Address
4AH
48H
49H
HT82B40R/HT82B40A
September 4, 2009
Data7~Data0
Data7~Data0
Data7~Data0
Bit7~Bit0