HT82B40A HOLTEK [Holtek Semiconductor Inc], HT82B40A Datasheet - Page 22

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HT82B40A

Manufacturer Part Number
HT82B40A
Description
I/O MCU with USB Interface
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet

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Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
Rev. 1.10
USB Interrupt
Timer/Event Counter 0 Overflow
Interrupt
Timer/Event Counter 1 Overflow
Interrupt
Interrupt Source
Priority
1
2
3
Vector
000CH
0004H
0008H
Interrupt Structure
INTC Register
22
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I/ET1I, must first be set. An ac-
tual Timer/Event Counter interrupt will take place when
the Timer/Event Counter interrupt request flag,
T0F/T1F, is set, a situation that will occur when the
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 08H/0CH, will take place. When the in-
terrupt is serviced, the timer interrupt request flag,
T0F/T1F, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
HT82B40R/HT82B40A
September 4, 2009

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