OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 5
![no-image](/images/no-image-200.jpg)
OX16PCI954-TQC60-A
Manufacturer Part Number
OX16PCI954-TQC60-A
Description
Integrated Quad UART and PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet
1.OX16PCI954-TQC60-A.pdf
(72 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
OX16PCI954-TQC60-A1
Manufacturer:
AD
Quantity:
556
1
Note 1:
Improvements of the OX16PCI954 over discrete solutions:
Higher degree of integration:
OX16PCI954 offers four internal 16C950 high-performance
UARTs and one bi-directional parallel port.
Improved access timing:
Access to internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
P
ERFORMANCE
Zero wait-state applies only to internal UARTs
Subsystem Vendor ID & Subsystem ID with
DWORD access to UART Interrupt Source
Full Plug and Play with external EEPROM
No. of available Local Bus interrupt pins
Table 1: OX16PCI950 performance compared with PLX + generic UART combinations
Support for PCI Power Management
Zero wait-state read/write operation
Max baud rate in 1x clock mode
Integral 1284 EPP parallel port
Readable status of flow control
Max baud rate in normal mode
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
External 1x baud rate clock
Transmitter empty interrupt
Multi-function PCI device
Registers & FIFO Levels
Clock prescaler options
Internal serial channels
Auto DSR#/DTR# flow
Auto CTS#/RTS# flow
C
Readable FIFO levels
no external EEPROM
RS485 buffer enable
Auto Xon/Xoff flow
OMPARISON
Good-Data status
9-bit data frames
Infra-red (IrDA)
Software reset
Rx/Tx disable
Sleep mode
FIFO depth
Device ID
Feature
OX16PCI954
15 Mbps
60 Mbps
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
OX16PCI954 offers shadowed FIFO levels and Interrupt
status registers of internal UARTs, and Interrupt Status of
internal UARTs and MIO pins to reduce the device driver
interrupt latency.
yes
128
128
128
128
248
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
12
4
1
16C554 +
PLX9050
115 Kbps
yes
n/a
n/a
n/a
no
no
no
no
no
no
no
no
16
no
no
no
no
no
no
no
no
no
no
no
no
no
0
2
4
1
16C654 +
PLX9050
1.5 Mbps
yes
yes
yes
yes
yes
n/a
no
no
no
no
no
no
no
no
64
no
no
no
no
no
no
no
no
no
0
2
4
4
4
2
OX16PCI954
Page 5