OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 19
![no-image](/images/no-image-200.jpg)
OX16PCI954-TQC60-A
Manufacturer Part Number
OX16PCI954-TQC60-A
Description
Integrated Quad UART and PCI interface
Manufacturer
OXFORD [Oxford Semiconductor]
Datasheet
1.OX16PCI954-TQC60-A.pdf
(72 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
OX16PCI954-TQC60-A1
Manufacturer:
AD
Quantity:
556
6.4.2
This register configures the operation of the multi-purpose I/O pins ‘MIO[11:0] as follows.
Data Sheet Revision 1.3
Bits
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
OXFORD SEMICONDUCTOR LTD.
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
Description
MIO0 Configuration Register (Mode[1:0] ‘01’).
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
Unused (Mode[1:0]=‘01’). When Parallel Port is enabled, MIO[0] pin is
unused and will remain in forcing output mode.
MIO1 Configuration Register (LCC[6:5]=‘00’).
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
Unused (LCC[6:5]
enabled, MIO1 pin is unused and will remain in forcing output mode.
MIO2 Configuration Register (LCC[7]=’0’).
00 -> MIO2 is a non-inverting input pin
01 -> MIO2 is an inverting input pin
10 -> MIO2 is output pin driving ‘0’
11 -> MIO2 is output pin driving ‘1’
PME_Input (LCC[7]=’1’). When LCC[7] is set, MIO2 pin is re-defined to
PME_Input. It’s polarity will be controlled by MIC[4]. It sets the sticky
PME_Status bit in Function1.
MIO3 Configuration Register.
00 -> MIO3 is a non-inverting input pin
01 -> MIO3 is an inverting input pin
10 -> MIO3 is an output pin driving ‘0’
11 -> MIO3 is an output pin driving ‘1’
MIO4 Configuration Register.
00 -> MIO4 is a non-inverting input pin
01 -> MIO4 is an inverting input pin
10 -> MIO4 is an output pin driving ‘0’
11 -> MIO4 is an output pin driving ‘1’
MIO5 Configuration Register.
00 -> MIO5 is a non-inverting input pin
01 -> MIO5 is an inverting input pin
10 -> MIO5 is an output pin driving ‘0’
11 -> MIO5 is an output pin driving ‘1’
MIO6 Configuration Register.
00 -> MIO6 is a non-inverting input pin
01 -> MIO6 is an inverting input pin
10 -> MIO6 is an output pin driving ‘0’
11 -> MIO6 is an output pin driving ‘1’
MIO7 Configuration Register.
00 -> MIO7 is a non-inverting input pin
01 -> MIO7 is an inverting input pin
10 -> MIO7 is an output pin driving ‘0’
11 -> MIO7 is an output pin driving ‘1’
‘00’). When power-down mode in Function0 is
EEPROM
W
W
W
W
W
W
W
W
Read/Write
PCI
RW
RW
RW
RW
RW
RW
RW
RW
OX16PCI954
Reset
Page 19
00
00
00
00
00
00
00
00