A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 71

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Figure 2-19 • Output Enable Register Timing Diagram
Table 2-96 • Output Enable Register Propagation Delays
Enable
CLK
D_Enable
Preset
EOUT
Clear
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Output Enable Register
Timing Characteristics
Automotive-Case Conditions: T
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width HIGH for the Output Enable Register
Clock Minimum Pulse Width LOW for the Output Enable Register
50%
50%
t
OESUE
1
t
OEHE
50%
t
OESUD
50%
t
0
OECLKQ
t
50%
OEHD
50%
50%
t
OEWPRE
J
= 135°C, Worst-Case V
t
Description
OEPRE2Q
50%
50%
v1.0
t
50%
OERECPRE
50%
Automotive ProASIC3 DC and Switching Characteristics
t
t
OEWCLR
OECLR2Q
50%
50%
CC
t
= 1.425 V
50%
OERECCLR
Table 2-5 on page 2-5
50%
t
OECKMPWH
t
OEREMPRE
50%
0.54 0.64
0.38 0.45
0.53 0.62
0.00 0.00
0.81 0.95
0.00 0.00
0.27 0.32
0.00 0.00
0.27 0.32
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
0.00 0.00
0.81 0.95
50%
t
–1
OECKMPWL
for derating
Std. Units
t
OEREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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