A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 24
A3P060-1VQ144T
Manufacturer Part Number
A3P060-1VQ144T
Description
Automotive ProASIC3 Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A3P060-1VQ144T.pdf
(136 pages)
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Automotive ProASIC3 DC and Switching Characteristics
User I/O Characteristics
Figure 2-3 • Timing Model
2 -1 2
I/O banks only)
to Advanced
(applicable
(Applicable for
Advanced I/O
LVPECL
t
Banks only)
PY
= 0.94 ns (Advanced I/O banks)
Clock
Input LVTTL
M-LVDS
BLVDS,
LVDS,
Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation
Timing Model
Component
β
β
β
Operating Conditions: –1 Speed, Automotive Grade 2 Temp. Range (T
V
1
2
3
CC
t
= 1.425 V
PY
(non-registered)
(registered)
I/O Module
= 1.29 ns
I/O Module
t
t
t
PY
ICLKQ
ISUD
= 1.47 ns
= 0.31 ns
= 0.29 ns
D
Q
I/O output buffer enable rate
RAM enable rate for read operations
RAM enable rate for write operations
Register Cell
t
t
CLKQ
SUD
D
= 0.51 ns
= 0.66 ns
Combinational Cell
Q
(Advanced I/O banks)
Combinational Cell
t
PD
Combinational Cell
t
Clock
PD
Input LVTTL
t
PY
= 1.04 ns
t
= 0.67 ns
PD
= 0.94 ns
= 0.56 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
v1.0
Y
= 0.60 ns
= 0.56 ns
Register Cell
Combinational Cell
t
t
CLKQ
SUD
Definition
D
t
PD
Y
= 0.51 ns
Y
(non-registered)
= 0.66 ns
= 0.58 ns
(Advanced I/O banks)
t
I/O Module
Q
DP
t
Clock
Input LVTTL
PY
= 3.25 ns (Advanced I/O banks)
(non-registered)
(non-registered)
t
t
I/O Module
I/O Module
DP
= 0.94 ns
DP
Y
= 4.89 ns (Advanced I/O banks)
= 4.52 ns (Advanced I/O banks)
(non-registered)
I/O Module
t
DP
LVTTL Output Drive Strength = 12 mA
= 1.66 ns
t
t
D
OCLKQ
OSUD
(registered)
I/O Module
LVTTL Output drive Strength = 8 mA
LVCMOS 1.5 V Output Drive Strength = 4 mA
High Slew Rate
Q
= 0.37 ns
= 0.70 ns
t
(Advanced I/O banks)
DP
High Slew Rate
J
= 3.25 ns
= 115°C), Worst Case
LVPECL (applicable to
Advanced I/O banks only)
High Slew Rate
LVTTL 3.3 V Output Drive
Strength = 12 mA
High Slew Rate
Guideline
12.5%
12.5%
100%
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