ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 31

• Manufacturer Part Number: ISPPACCLK5316S-01T48C
• Description: In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 25. Maximum Ambient Temperature vs. Number of Active Output Banks
Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced
airflow present in a given design, actual die operating temperature is subject to considerable variation from that
which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls (OEX, OEY)
The ispClock5300S family provides two output control pins for enabling and disabling clock outputs. In addition, the
outputs can also be configured to be permanently enabled or permanently disabled.
Skew Control Units
Each of the ispClock5300S’s clock outputs is supported by a skew control unit which allows the user to insert an
individually programmable delay into each output signal. This feature is useful when it is necessary to de-skew
clock signals to compensate for physical length variations among different PCB clock paths.
The ispClock5300S’s skew adjustment feature provides exact and repeatable delays which exhibit extremely low
channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the VCO,
which results in the skew increment being a linear function of the VCO period. For this reason, skews are defined in
terms of ‘unit delays’, which may be programmed by the user over a range of 0 to 7. The ispClock5300S family also
supports both ‘fine’ and ‘coarse’ skew modes. In fine skew mode, the unit skew ranges from 156ps to 390 ps, while
in the coarse skew mode unit skew varies from 312ps to 780ps. The exact unit skew (TU) may be calculated from
the VCO frequency (f
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5300S family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides unit delays ranging from 312ps
90
80
70
60
50
40
30
20
10
0
Outputs LVCMOS33, 3.3V, f
1
(ispClock 5304S, 5308S, 5312S)
Temperature Derating Curves
2
Number of Active Banks
vco
) by using the following expressions:
For fine skew mode,
3
OUT
4
= 100MHz Still Air
5312S Commercial
5312S Industrial
TU
5
=
16f
1
vco
6
31
90
80
70
60
50
40
30
For coarse skew mode,
0
Outputs LVCMOS33, 3.3V, f
ispClock5300S Family Data Sheet
2
Temperature Derating Curves
Number of Active Banks
(ispClock 5316S, 5320S)
TU
4
=
8f
1
vco
6
5320S Commercial
OUT
5320S Industrial
= 100MHz Still Air
8
10
12
(5)