ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 27
ISPPACCLK5316S-01T48C
Manufacturer Part Number
ISPPACCLK5316S-01T48C
Description
In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
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Lattice Semiconductor
Figure 22. ispClock5300S configured as Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Figure 23 shows the operation of the ispClock5300S in Mixed Zero Delay and Non Zero Delay modes. In this mode
the output switch matrix is configured to route non selected reference clock, selected reference clock, and the zero
delay clock through the PLL.
The skew control mechanism is available only to clocks sourced from the PLL.
Single Ended /
Clock Input
Differential
ispClock5300S
Internal Feedback
PLL
27
V1
V2
V3
External Feedback
ispClock5300S Family Data Sheet
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