WM9715LGEFLV WOLFSON [Wolfson Microelectronics plc], WM9715LGEFLV Datasheet - Page 53

• Manufacturer Part Number: WM9715LGEFLV
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Production Data
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The processing of internal interrupt signals is controlled through registers 4Eh to 52h, as shown
below.
Table 38 GENIRQ Interrupt Control
The following procedure is recommended for handling GENIRQ interrupts:
When the controller receives a GENIRQ interrupt, check register 54h. For each interrupt event in
descending order of priority, check if the corresponding xI bit in 54h is ‘1’. If yes, execute
corresponding interrupt routine, then write ‘0’ to the xI bit. If no, continue to next lower priority
interrupt. After all interrupts have been checked, check if the global interrupt is still asserted. If yes,
repeat procedure. If no, jump back to process that ran before the interrupt.
Note: x identifies a particular interrupt (T, A, P, C2 or C1, as per Table 37)
4Eh
50h
52h
54h
REGISTER
ADDRESS
LABEL DEFAULT
xW
xP
xS
xI
N/A
1
0
0
Interrupt Polarity
0: Active Low
1: Active High
[xI bit = internal interrupt signal XNOR xP]
Interrupt Sticky
1: Sticky (GIn bit remains set until read, even after internal
0: Not Sticky (GIn bit follows internal interrupt signal)
Interrupt Enable
1: Wake Up (generate interrupts from this pin)
0: No wake-up (no interrupts generated)
Interrupt Status
Read: Returns status of each interrupt bit
Write: Writing ‘0’ clears sticky bit
interrupt signal becomes inactive)
DESCRIPTION
PD Rev 4.0 December 2007
WM9715L
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