NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet - Page 35

• Manufacturer Part Number: NS16C2552TVA
• Description: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
• Manufacturer: NSC [National Semiconductor]

8.0 Design Notes
4. The load capacitance of the crystal should match the
It should be noted that the parasitic capacitance also include
printed circuit board traces. The circuit board traces connect-
ing to the crystal should be kept as short as possible.
8.4 CONFIGURATION EXAMPLES
8.4.1 Set Baud Rate
Set divisor values to DIV_L and DIV_M.
8.4.2 Configure Prescaler Output
Set prescaler output to XIN divide by 4.
Set prescaler output to XIN divide by 1.
• LCR 0x03.7 = 1
• DLL 0x00.7:0 = DIV_L
• DLM 0x01.7:0 = DIV_M
• LCR 0x03.7 = 0
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.4 = 1
• LCR 0x03.7:0 = 0
• MCR 0x04.7 = 1
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.4 = 0 (optional)
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
load capacitance of the oscillator circuitry seen by the
crystal. Under the AC conditions, the oscillator load ca-
pacitance is a lump sum of parasitic capacitance and
external capacitors. The capacitances connecting to os-
cillator input and output are in series seen by the crystal.
(Figure 16.) External capacitors, C1 and C2, are not
required to be very accurate. The best practice to follow
crystal manufacturer’s recommendation for the load ca-
pacitance value.
FIGURE 16. Crystal Oscillator Circuit
(Continued)
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8.4.3 Set Xon and Xoff flow control
Set Xon1, Xoff1 to VAL1 and VAL2.
Set Xon2, Xoff2 to VAL1 and VAL2.
8.4.4 Set Software Flow Control
Set software flow control mode to VAL.
8.4.5 Configure Tx/Rx FIFO Threshold
Set Tx (2752) and Rx FIFO thresholds to VAL.
8.4.6 Tx and Rx Hardware Flow Control
Configure auto RTS and CTS flow controls, enable RTS and
CTS interrupts, and assert RTS.
8.4.7 Tx and Rx DMA Control
Configure Tx and Rx in FIFO mode DMA transfers using the
threshold in FCR[7:4].
• EFR 0x02.4 = 1
• LCR 0x03.7:0 = 0
• MCR 0x04.7 = 0
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.4 = 0 (optional)
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• Xon1 0x04.7:0 = VAL1
• Xoff1 0x06.7:0 = VAL2
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• Xon2 0x05.7:0 = VAL1
• Xoff2 0x07.7:0 = VAL2
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.3:0 = VAL
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.4 = 1
• LCR 0x03.7:0 = 0
• FCR 0x02.7:0 = VAL
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.4 = 0 (optional)
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0xBF
• EFR 0x02.7:6 = 2b’11
• EFR 0x02.4 = 1
• LCR 0x03.7:0 = 0
• IER 0x01.7:6 = 2b’11
• MCR 0x04.1 = 1
• LCR 0x03.7:0 = temp
• Save LCR 0x03.7:0 in temp
• LCR 0x03.7:0 = 0
• FCR 0x02.0 = 1
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