NS16C2552TVA NSC [National Semiconductor], NS16C2552TVA Datasheet - Page 20

• Manufacturer Part Number: NS16C2552TVA
• Description: Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
• Manufacturer: NSC [National Semiconductor]

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6.0 Register Set
6.8 LINE STATUS REGISTER (LSR)
This register provides status information to the CPU con-
cerning the data transfer.
Bit
7
6
5
4
Rx FIFO Err
THR & TSR
THR Empty
Bit Name
Rx Break
Interrupt
Empty
(Continued)
R/W
Def
R
R
R
R
0
1
1
0
Rx FIFO Data Error
This bit is a global Rx FIFO error flag. In the 16450 Mode this bit is 0.
1 = A sum of all error bits in the Rx FIFO. These errors include parity, framing, and
break indication in the FIFO data.
0 = No Rx FIFO error (default).
Note: The Line Status Register is intended for read operations only. Writing to this register is not recommended
THR and TSR Empty
This bit is the Transmitter Empty (TEMT) flag.
1 = Whenever the Transmitter Holding Register (THR) (or the Tx FIFO in FIFO mode)
and the Transmitter Shift Register (TSR) are both empty (default).
0 = Whenever either the THR (or the Tx FIFO in FIFO mode) or the TSR contains a
data word.
THR Empty
This bit is the Transmitter Holding Register Empty (THRE) flag. In the 16450 mode bit
5 indicates that the associated serial channel is ready to accept a new character for
transmission. In addition, this bit causes the DUART to issue an interrupt to the CPU
when the Transmit Holding Register Empty interrupt enable is set.
1 = In 16450 mode, whenever a character is transferred from the Transmitter Holding
Register into the Transmitter Shift Register, or in FIFO mode when the Tx FIFO is
empty (default).
0 = In 16450 mode, this bit is reset to logic 0 concurrently with the loading of the
Transmitter Holding Register by the CPU. In FIFO mode, it is cleared when at least 1
byte is written to the Tx FIFO.
Receive Break Interrupt Indicator
This bit is the Break Interrupt (BI) indicator.
1 = Whenever the received data input is held in the Spacing (logic 0) state for longer
than a full frame transmission time (that is, the total time of Start bit + data bits +
Parity + Stop bits).
0 = No break condition (default).
This bit is reset to 0 whenever the CPU reads the contents of the Line Status Register
or when the next valid character is loaded into the Receiver Buffer Register.
In the FIFO Mode this condition is associated with the particular character in the FIFO
it applies to. It is revealed to the CPU when its associated character is at the top of
the FIFO. When break occurs only one zero character is loaded into the FIFO. The
next character transfer is enabled after SIN goes to the Marking (logic 1) state and
receives the next valid start bit.
as this operation is only used for factory testing.
TABLE 12. LSR (0x5)
20
Bits 1 through 4 are the error conditions that produce a
Receiver Line Status interrupt whenever any of the corre-
sponding conditions are detected and the interrupt is en-
abled.
Description